From 5c51b6334ffc90768ed66e85685848c5e9c69959 Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 13:41:08 -0400 Subject: [PATCH 01/14] rename Node to node --- libs/libarchfpga/src/read_xml_arch_file.cpp | 378 ++++++++++---------- 1 file changed, 189 insertions(+), 189 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 79c6a46e6d..5c2df12772 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -137,7 +137,7 @@ static std::pair process_instance_string(pugi::xml_node Locations, const pugiutil::loc_data& loc_data); /* Process XML hierarchy */ -static void process_tiles(pugi::xml_node Node, +static void process_tiles(pugi::xml_node node, std::vector& PhysicalTileTypes, std::vector& LogicalBlockTypes, const t_default_fc_spec& arch_def_fc, @@ -150,7 +150,7 @@ static void process_tiles(pugi::xml_node Node, // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193 static void mark_IO_types(std::vector& PhysicalTileTypes); -static void process_tile_props(pugi::xml_node Node, +static void process_tile_props(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, const pugiutil::loc_data& loc_data); @@ -158,7 +158,7 @@ static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, t_sub_tile* SubTile, const pugiutil::loc_data& loc_data); -static void process_tile_port(pugi::xml_node Node, +static void process_tile_port(pugi::xml_node node, t_physical_tile_port* port, const pugiutil::loc_data& loc_data); @@ -185,7 +185,7 @@ static void process_pin_locations(pugi::xml_node Locations, const pugiutil::loc_data& loc_data, const int num_of_avail_layer); -static void process_sub_tiles(pugi::xml_node Node, +static void process_sub_tiles(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, std::vector& LogicalBlockTypes, std::vector& segments, @@ -262,8 +262,8 @@ static void process_mode(pugi::xml_node Parent, const pugiutil::loc_data& loc_data, int& parent_pb_idx); -static void process_fc_values(pugi::xml_node Node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data); -static void process_fc(pugi::xml_node Node, +static void process_fc_values(pugi::xml_node node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data); +static void process_fc(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, t_sub_tile* SubTile, t_pin_counts pin_counts, @@ -289,16 +289,16 @@ static void process_switch_block_locations(pugi::xml_node switchblock_locations, const pugiutil::loc_data& loc_data); static e_fc_value_type string_to_fc_value_type(const std::string& str, pugi::xml_node node, const pugiutil::loc_data& loc_data); -static void process_chan_width_distr(pugi::xml_node Node, +static void process_chan_width_distr(pugi::xml_node node, t_arch* arch, const pugiutil::loc_data& loc_data); -static void process_chan_width_distr_dir(pugi::xml_node Node, t_chan* chan, const pugiutil::loc_data& loc_data); -static void process_models(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); +static void process_chan_width_distr_dir(pugi::xml_node node, t_chan* chan, const pugiutil::loc_data& loc_data); +static void process_models(pugi::xml_node node, t_arch* arch, const pugiutil::loc_data& loc_data); static void process_model_ports(pugi::xml_node port_group, t_model& model, std::set& port_names, const pugiutil::loc_data& loc_data); -static void process_layout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data, int& num_of_avail_layer); +static void process_layout(pugi::xml_node node, t_arch* arch, const pugiutil::loc_data& loc_data, int& num_of_avail_layer); static t_grid_def process_grid_layout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); static void process_block_type_locs(t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); -static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data); +static void process_device(pugi::xml_node node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data); /** * @brief Parses tags related to tileable rr graph under tag in the architecture file. @@ -308,24 +308,24 @@ static void process_tileable_device_parameters(t_arch* arch, const pugiutil::loc /** * @brief Parses tag in the architecture file. * - * @param Node The xml node referring to tag + * @param node The xml node referring to tag * @param LogicalBlockTypes This function fills this vector with all available * logical block types. * @param arch Used to access models and string internment storage. * @param timing_enabled Determines whether timing-aware optimizations are enabled. * @param loc_data Points to the location in the xml file where the parser is reading. */ -static void process_complex_blocks(pugi::xml_node Node, +static void process_complex_blocks(pugi::xml_node node, std::vector& LogicalBlockTypes, const t_arch& arch, bool timing_enabled, const pugiutil::loc_data& loc_data); -static std::vector process_switches(pugi::xml_node Node, +static std::vector process_switches(pugi::xml_node node, const bool timing_enabled, const pugiutil::loc_data& loc_data); -static void process_switch_tdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data); +static void process_switch_tdel(pugi::xml_node node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data); static std::vector process_directs(pugi::xml_node Parent, const std::vector& switches, @@ -355,7 +355,7 @@ static std::vector process_segments(pugi::xml_node parent, const pugiutil::loc_data& loc_data); static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data); -static void process_cb_sb(pugi::xml_node Node, std::vector& list, const pugiutil::loc_data& loc_data); +static void process_cb_sb(pugi::xml_node node, std::vector& list, const pugiutil::loc_data& loc_data); static void process_power(pugi::xml_node parent, t_power_arch* power_arch, const pugiutil::loc_data& loc_data); @@ -385,7 +385,7 @@ static e_side string_to_side(const std::string& side_str); template static T* get_type_by_name(std::string_view type_name, std::vector& types); -static void process_bend(pugi::xml_node Node, t_segment_inf& segment, const int len, const pugiutil::loc_data& loc_data); +static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int len, const pugiutil::loc_data& loc_data); /* * @@ -1999,27 +1999,27 @@ static void process_mode(pugi::xml_node Parent, process_interconnect(arch.strings, Cur, mode, loc_data); } -static void process_fc_values(pugi::xml_node Node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data) { +static void process_fc_values(pugi::xml_node node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data) { spec.specified = true; /* Load the default fc_in */ - auto default_fc_in_attrib = get_attribute(Node, "in_type", loc_data); - spec.in_value_type = string_to_fc_value_type(default_fc_in_attrib.value(), Node, loc_data); + auto default_fc_in_attrib = get_attribute(node, "in_type", loc_data); + spec.in_value_type = string_to_fc_value_type(default_fc_in_attrib.value(), node, loc_data); - auto in_val_attrib = get_attribute(Node, "in_val", loc_data); + auto in_val_attrib = get_attribute(node, "in_val", loc_data); spec.in_value = vtr::atof(in_val_attrib.value()); /* Load the default fc_out */ - auto default_fc_out_attrib = get_attribute(Node, "out_type", loc_data); - spec.out_value_type = string_to_fc_value_type(default_fc_out_attrib.value(), Node, loc_data); + auto default_fc_out_attrib = get_attribute(node, "out_type", loc_data); + spec.out_value_type = string_to_fc_value_type(default_fc_out_attrib.value(), node, loc_data); - auto out_val_attrib = get_attribute(Node, "out_val", loc_data); + auto out_val_attrib = get_attribute(node, "out_val", loc_data); spec.out_value = vtr::atof(out_val_attrib.value()); } /* Takes in the node ptr for the 'fc' elements and initializes * the appropriate fields of type. */ -static void process_fc(pugi::xml_node Node, +static void process_fc(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, t_sub_tile* SubTile, t_pin_counts pin_counts, @@ -2028,18 +2028,18 @@ static void process_fc(pugi::xml_node Node, const pugiutil::loc_data& loc_data) { std::vector fc_overrides; t_default_fc_spec def_fc_spec; - if (Node) { + if (node) { /* Load the default Fc values from the node */ - process_fc_values(Node, def_fc_spec, loc_data); + process_fc_values(node, def_fc_spec, loc_data); /* Load any tags */ - for (auto child_node : Node.children()) { + for (auto child_node : node.children()) { t_fc_override fc_override = process_fc_override(child_node, loc_data); fc_overrides.push_back(fc_override); } } else { /* Use the default value, if available */ if (!arch_def_fc.specified) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt(" is missing child , and no specified in architecture\n").c_str()); } def_fc_spec = arch_def_fc; @@ -2102,7 +2102,7 @@ static void process_fc(pugi::xml_node Node, if (default_overriden) { //Warn if multiple overrides match - VTR_LOGF_WARN(loc_data.filename_c_str(), loc_data.line(Node), "Multiple matching Fc overrides found; the last will be applied\n"); + VTR_LOGF_WARN(loc_data.filename_c_str(), loc_data.line(node), "Multiple matching Fc overrides found; the last will be applied\n"); } fc_spec.fc_value_type = fc_override.fc_value_type; @@ -2369,15 +2369,15 @@ static void process_switch_block_locations(pugi::xml_node switchblock_locations, /* Takes in node pointing to and loads all the * child type objects. */ -static void process_models(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data) { +static void process_models(pugi::xml_node node, t_arch* arch, const pugiutil::loc_data& loc_data) { pugi::xml_node p; /* std::maps for checking duplicates */ std::map model_name_map; - for (pugi::xml_node model : Node.children()) { + for (pugi::xml_node model : node.children()) { //Process each model if (model.name() != std::string("model")) { - bad_tag(model, loc_data, Node, {"model"}); + bad_tag(model, loc_data, node, {"model"}); } try { @@ -2901,7 +2901,7 @@ static void process_block_type_locs(t_grid_def& grid_def, /* Takes in node pointing to and loads all the * child type objects. */ -static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data) { +static void process_device(pugi::xml_node node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data) { const char* Prop; pugi::xml_node Cur; bool custom_switch_block = false; @@ -2909,7 +2909,7 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& //Warn that is no longer supported //TODO: eventually remove try { - expect_child_node_count(Node, "timing", 0, loc_data); + expect_child_node_count(node, "timing", 0, loc_data); } catch (pugiutil::XmlError& e) { std::string msg = e.what(); msg += ". has been replaced with the tag."; @@ -2917,30 +2917,30 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& archfpga_throw(e.filename().c_str(), e.line(), msg.c_str()); } - expect_only_children(Node, {"sizing", "area", "chan_width_distr", "switch_block", "connection_block", "default_fc"}, loc_data); + expect_only_children(node, {"sizing", "area", "chan_width_distr", "switch_block", "connection_block", "default_fc"}, loc_data); // tag - Cur = get_single_child(Node, "sizing", loc_data); + Cur = get_single_child(node, "sizing", loc_data); expect_only_attributes(Cur, {"R_minW_nmos", "R_minW_pmos"}, loc_data); arch->R_minW_nmos = get_attribute(Cur, "R_minW_nmos", loc_data).as_float(); arch->R_minW_pmos = get_attribute(Cur, "R_minW_pmos", loc_data).as_float(); // tag - Cur = get_single_child(Node, "area", loc_data); + Cur = get_single_child(node, "area", loc_data); expect_only_attributes(Cur, {"grid_logic_tile_area"}, loc_data); arch->grid_logic_tile_area = get_attribute(Cur, "grid_logic_tile_area", loc_data, ReqOpt::OPTIONAL) .as_float(0); // tag - Cur = get_single_child(Node, "chan_width_distr", loc_data, ReqOpt::OPTIONAL); + Cur = get_single_child(node, "chan_width_distr", loc_data, ReqOpt::OPTIONAL); expect_only_attributes(Cur, {}, loc_data); if (Cur != nullptr) { process_chan_width_distr(Cur, arch, loc_data); } // tag - Cur = get_single_child(Node, "connection_block", loc_data); + Cur = get_single_child(node, "connection_block", loc_data); expect_only_attributes(Cur, {"input_switch_name", "input_inter_die_switch_name"}, loc_data); arch->ipin_cblock_switch_name.emplace_back(get_attribute(Cur, "input_switch_name", loc_data).as_string()); std::string inter_die_conn = get_attribute(Cur, "input_inter_die_switch_name", loc_data, ReqOpt::OPTIONAL).as_string(""); @@ -2949,7 +2949,7 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& } // tag - Cur = get_single_child(Node, "switch_block", loc_data); + Cur = get_single_child(node, "switch_block", loc_data); expect_only_attributes(Cur, {"type", "fs", "sub_type", "sub_fs"}, loc_data); Prop = get_attribute(Cur, "type", loc_data).value(); // Parse attribute 'type', representing the major connectivity pattern for switch blocks @@ -2972,7 +2972,7 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& process_tileable_device_parameters(arch, loc_data); - Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL); + Cur = get_single_child(node, "default_fc", loc_data, ReqOpt::OPTIONAL); if (Cur) { arch_def_fc.specified = true; expect_only_attributes(Cur, {"in_type", "in_val", "out_type", "out_val"}, loc_data); @@ -3011,29 +3011,29 @@ static void process_tileable_device_parameters(t_arch* arch, const pugiutil::loc /* Takes in node pointing to and loads all the * child type objects. */ -static void process_chan_width_distr(pugi::xml_node Node, +static void process_chan_width_distr(pugi::xml_node node, t_arch* arch, const pugiutil::loc_data& loc_data) { pugi::xml_node Cur; - expect_only_children(Node, {"x", "y"}, loc_data); + expect_only_children(node, {"x", "y"}, loc_data); - Cur = get_single_child(Node, "x", loc_data); + Cur = get_single_child(node, "x", loc_data); process_chan_width_distr_dir(Cur, &arch->Chans.chan_x_dist, loc_data); - Cur = get_single_child(Node, "y", loc_data); + Cur = get_single_child(node, "y", loc_data); process_chan_width_distr_dir(Cur, &arch->Chans.chan_y_dist, loc_data); } /* Takes in node within and loads all the * child type objects. */ -static void process_chan_width_distr_dir(pugi::xml_node Node, t_chan* chan, const pugiutil::loc_data& loc_data) { +static void process_chan_width_distr_dir(pugi::xml_node node, t_chan* chan, const pugiutil::loc_data& loc_data) { const char* Prop; ReqOpt hasXpeak, hasWidth, hasDc; hasXpeak = hasWidth = hasDc = ReqOpt::OPTIONAL; - Prop = get_attribute(Node, "distr", loc_data).value(); + Prop = get_attribute(node, "distr", loc_data).value(); if (strcmp(Prop, "uniform") == 0) { chan->type = e_stat::UNIFORM; } else if (strcmp(Prop, "gaussian") == 0) { @@ -3046,17 +3046,17 @@ static void process_chan_width_distr_dir(pugi::xml_node Node, t_chan* chan, cons hasXpeak = hasDc = ReqOpt::REQUIRED; chan->type = e_stat::DELTA; } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Unknown property %s for chan_width_distr x\n", Prop).c_str()); } - chan->peak = get_attribute(Node, "peak", loc_data).as_float(ARCH_FPGA_UNDEFINED_VAL); - chan->width = get_attribute(Node, "width", loc_data, hasWidth).as_float(0); - chan->xpeak = get_attribute(Node, "xpeak", loc_data, hasXpeak).as_float(0); - chan->dc = get_attribute(Node, "dc", loc_data, hasDc).as_float(0); + chan->peak = get_attribute(node, "peak", loc_data).as_float(ARCH_FPGA_UNDEFINED_VAL); + chan->width = get_attribute(node, "width", loc_data, hasWidth).as_float(0); + chan->xpeak = get_attribute(node, "xpeak", loc_data, hasXpeak).as_float(0); + chan->dc = get_attribute(node, "dc", loc_data, hasDc).as_float(0); } -static void process_tiles(pugi::xml_node Node, +static void process_tiles(pugi::xml_node node, std::vector& PhysicalTileTypes, std::vector& LogicalBlockTypes, const t_default_fc_spec& arch_def_fc, @@ -3077,7 +3077,7 @@ static void process_tiles(pugi::xml_node Node, /* Process the types */ int index = 1; /* Skip over 'empty' type */ - pugi::xml_node CurTileType = Node.first_child(); + pugi::xml_node CurTileType = node.first_child(); while (CurTileType) { check_node(CurTileType, "tile", loc_data); @@ -3145,22 +3145,22 @@ static void mark_IO_types(std::vector& PhysicalTileTypes) } } -static void process_tile_props(pugi::xml_node Node, +static void process_tile_props(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, const pugiutil::loc_data& loc_data) { - expect_only_attributes(Node, {"name", "width", "height", "area"}, loc_data); + expect_only_attributes(node, {"name", "width", "height", "area"}, loc_data); /* Load type name */ - auto Prop = get_attribute(Node, "name", loc_data).value(); + auto Prop = get_attribute(node, "name", loc_data).value(); PhysicalTileType->name = Prop; /* Load properties */ - PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); - PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1); - PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); + PhysicalTileType->width = get_attribute(node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); + PhysicalTileType->height = get_attribute(node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1); + PhysicalTileType->area = get_attribute(node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); if (atof(Prop) < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Area for type %s must be non-negative\n", PhysicalTileType->name.c_str()).c_str()); } } @@ -3232,71 +3232,71 @@ static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, return pin_counts; } -static void process_tile_port(pugi::xml_node Node, +static void process_tile_port(pugi::xml_node node, t_physical_tile_port* port, const pugiutil::loc_data& loc_data) { std::vector expected_attributes = {"name", "num_pins", "equivalent"}; - if (Node.name() == "input"s || Node.name() == "clock"s) { + if (node.name() == "input"s || node.name() == "clock"s) { expected_attributes.emplace_back("is_non_clock_global"); } - expect_only_attributes(Node, expected_attributes, loc_data); + expect_only_attributes(node, expected_attributes, loc_data); const char* Prop; - Prop = get_attribute(Node, "name", loc_data).value(); + Prop = get_attribute(node, "name", loc_data).value(); port->name = vtr::strdup(Prop); - Prop = get_attribute(Node, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + Prop = get_attribute(node, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { if (Prop == "none"s) { port->equivalent = PortEquivalence::NONE; } else if (Prop == "full"s) { port->equivalent = PortEquivalence::FULL; } else if (Prop == "instance"s) { - if (Node.name() == "output"s) { + if (node.name() == "output"s) { port->equivalent = PortEquivalence::INSTANCE; } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), - vtr::string_fmt("Invalid pin equivalence '%s' for %s port.", Prop, Node.name()).c_str()); + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), + vtr::string_fmt("Invalid pin equivalence '%s' for %s port.", Prop, node.name()).c_str()); } } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Invalid pin equivalence '%s'.", Prop).c_str()); } } - port->num_pins = get_attribute(Node, "num_pins", loc_data).as_int(0); - port->is_non_clock_global = get_attribute(Node, + port->num_pins = get_attribute(node, "num_pins", loc_data).as_int(0); + port->is_non_clock_global = get_attribute(node, "is_non_clock_global", loc_data, ReqOpt::OPTIONAL) .as_bool(false); if (port->num_pins <= 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), - vtr::string_fmt("Invalid number of pins %d for %s port.", port->num_pins, Node.name()).c_str()); + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), + vtr::string_fmt("Invalid number of pins %d for %s port.", port->num_pins, node.name()).c_str()); } - if (0 == strcmp(Node.name(), "input")) { + if (0 == strcmp(node.name(), "input")) { port->type = IN_PORT; port->is_clock = false; - } else if (0 == strcmp(Node.name(), "output")) { + } else if (0 == strcmp(node.name(), "output")) { port->type = OUT_PORT; port->is_clock = false; - } else if (0 == strcmp(Node.name(), "clock")) { + } else if (0 == strcmp(node.name(), "clock")) { port->type = IN_PORT; port->is_clock = true; if (port->is_non_clock_global) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Port %s cannot be both a clock and a non-clock simultaneously\n", - Node.name()) + node.name()) .c_str()); } } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), - vtr::string_fmt("Unknown port type %s", Node.name()).c_str()); + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), + vtr::string_fmt("Unknown port type %s", node.name()).c_str()); } } @@ -3656,7 +3656,7 @@ static void process_pin_locations(pugi::xml_node Locations, } } -static void process_sub_tiles(pugi::xml_node Node, +static void process_sub_tiles(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, std::vector& LogicalBlockTypes, std::vector& segments, @@ -3666,7 +3666,7 @@ static void process_sub_tiles(pugi::xml_node Node, pugi::xml_node CurSubTile; pugi::xml_node Cur; - unsigned long int num_sub_tiles = count_children(Node, "sub_tile", loc_data); + unsigned long int num_sub_tiles = count_children(node, "sub_tile", loc_data); unsigned long int width = PhysicalTileType->width; unsigned long int height = PhysicalTileType->height; unsigned long int num_sides = 4; @@ -3675,7 +3675,7 @@ static void process_sub_tiles(pugi::xml_node Node, pin_locs.assignments.resize({num_sub_tiles, width, height, (unsigned long int)num_of_avail_layer, num_sides}); if (num_sub_tiles == 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("No sub tile found for the Physical Tile %s.\n" "At least one sub tile is needed to correctly describe the Physical Tile.\n", PhysicalTileType->name.c_str()) @@ -3688,7 +3688,7 @@ static void process_sub_tiles(pugi::xml_node Node, // used to assign indices to subtiles int subtile_index = 0; - CurSubTile = get_first_child(Node, "sub_tile", loc_data); + CurSubTile = get_first_child(node, "sub_tile", loc_data); while (CurSubTile) { t_sub_tile SubTile; @@ -3767,7 +3767,7 @@ static void process_sub_tiles(pugi::xml_node Node, /* Takes in node pointing to and loads all the * child type objects. */ -static void process_complex_blocks(pugi::xml_node Node, +static void process_complex_blocks(pugi::xml_node node, std::vector& LogicalBlockTypes, const t_arch& arch, const bool timing_enabled, @@ -3788,7 +3788,7 @@ static void process_complex_blocks(pugi::xml_node Node, /* Process the types */ int index = 1; /* Skip over 'empty' type */ - CurBlockType = Node.first_child(); + CurBlockType = node.first_child(); while (CurBlockType) { int pb_type_idx = 0; @@ -3837,7 +3837,7 @@ static std::vector process_segments(pugi::xml_node parent, std::vector Segs; pugi::xml_node SubElem; - pugi::xml_node Node; + pugi::xml_node node; // Count the number of segs specified in the architecture file. int num_segs = count_children(parent, "segment", loc_data); @@ -3848,7 +3848,7 @@ static std::vector process_segments(pugi::xml_node parent, } // Load the segments. - Node = get_first_child(parent, "segment", loc_data); + node = get_first_child(parent, "segment", loc_data); bool x_axis_seg_found = false; // Flags to see if we have any x-directed segment type specified bool y_axis_seg_found = false; // Flags to see if we have any y-directed segment type specified @@ -3856,13 +3856,13 @@ static std::vector process_segments(pugi::xml_node parent, for (int i = 0; i < num_segs; ++i) { /* Get segment name */ - tmp = get_attribute(Node, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + tmp = get_attribute(node, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { Segs[i].name = std::string(tmp); } else { /* if swich block is "custom", then you have to provide a name for segment */ if (switchblocklist_required) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("No name specified for the segment #%d.\n", i).c_str()); } /* set name to default: "unnamed_segment_" */ @@ -3875,7 +3875,7 @@ static std::vector process_segments(pugi::xml_node parent, /* Get segment length */ int length = 1; /* DEFAULT */ - tmp = get_attribute(Node, "length", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + tmp = get_attribute(node, "length", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { if (strcmp(tmp, "longline") == 0) { Segs[i].longline = true; @@ -3887,20 +3887,20 @@ static std::vector process_segments(pugi::xml_node parent, /* Get the frequency */ Segs[i].frequency = 1; /* DEFAULT */ - tmp = get_attribute(Node, "freq", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + tmp = get_attribute(node, "freq", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { Segs[i].frequency = (int)(atof(tmp) * MAX_CHANNEL_WIDTH); } /* Get timing info */ ReqOpt TIMING_ENABLE_REQD = BoolToReqOpt(timing_enabled); - Segs[i].Rmetal = get_attribute(Node, "Rmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); - Segs[i].Cmetal = get_attribute(Node, "Cmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); + Segs[i].Rmetal = get_attribute(node, "Rmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); + Segs[i].Cmetal = get_attribute(node, "Cmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); /*Get parallel axis*/ Segs[i].parallel_axis = e_parallel_axis::BOTH_AXIS; // DEFAULT value if no axis is specified - tmp = get_attribute(Node, "axis", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + tmp = get_attribute(node, "axis", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { if (strcmp(tmp, "x") == 0) { @@ -3913,7 +3913,7 @@ static std::vector process_segments(pugi::xml_node parent, Segs[i].parallel_axis = e_parallel_axis::Z_AXIS; z_axis_seg_found = true; } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Unsupported parallel axis type: %s\n", tmp).c_str()); } } else { @@ -3922,21 +3922,21 @@ static std::vector process_segments(pugi::xml_node parent, } // Get segment resource type - tmp = get_attribute(Node, "res_type", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + tmp = get_attribute(node, "res_type", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { auto it = std::find(RES_TYPE_STRING.begin(), RES_TYPE_STRING.end(), tmp); if (it != RES_TYPE_STRING.end()) { Segs[i].res_type = static_cast(std::distance(RES_TYPE_STRING.begin(), it)); } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Unsupported segment res_type: %s\n", tmp).c_str()); } } /* Get Power info */ /* - * (*Segs)[i].Cmetal_per_m = get_attribute(Node, "Cmetal_per_m", false, + * (*Segs)[i].Cmetal_per_m = get_attribute(node, "Cmetal_per_m", false, * 0.);*/ // Set of expected subtags (exact subtags are dependent on parameters) @@ -3949,7 +3949,7 @@ static std::vector process_segments(pugi::xml_node parent, } // Get the type - tmp = get_attribute(Node, "type", loc_data).value(); + tmp = get_attribute(node, "type", loc_data).value(); if (0 == strcmp(tmp, "bidir")) { Segs[i].directionality = BI_DIRECTIONAL; @@ -3973,15 +3973,15 @@ static std::vector process_segments(pugi::xml_node parent, } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Invalid switch type '%s'.\n", tmp).c_str()); } //Verify only expected sub-tags are found - expect_only_children(Node, expected_subtags, loc_data); + expect_only_children(node, expected_subtags, loc_data); //Get the switch name for different dice wire and track connections - SubElem = get_single_child(Node, "mux_inter_die", loc_data, ReqOpt::OPTIONAL); + SubElem = get_single_child(node, "mux_inter_die", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(""); if (strlen(tmp) != 0) { /* Match names */ @@ -3996,7 +3996,7 @@ static std::vector process_segments(pugi::xml_node parent, /* Get the wire and opin switches, or mux switch if unidir */ if (UNI_DIRECTIONAL == Segs[i].directionality) { //Get the switch name for same die wire and track connections - SubElem = get_single_child(Node, "mux", loc_data, ReqOpt::OPTIONAL); + SubElem = get_single_child(node, "mux", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); //check if tag is defined in the architecture, otherwise we should look for and @@ -4014,7 +4014,7 @@ static std::vector process_segments(pugi::xml_node parent, Segs[i].arch_wire_switch = switch_idx; Segs[i].arch_opin_switch = switch_idx; } else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file - SubElem = get_single_child(Node, "mux_inc", loc_data, ReqOpt::OPTIONAL); + SubElem = get_single_child(node, "mux_inc", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (!tmp) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), @@ -4034,7 +4034,7 @@ static std::vector process_segments(pugi::xml_node parent, Segs[i].arch_opin_switch = switch_idx; } - SubElem = get_single_child(Node, "mux_dec", loc_data, ReqOpt::OPTIONAL); + SubElem = get_single_child(node, "mux_dec", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (!tmp) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), @@ -4056,7 +4056,7 @@ static std::vector process_segments(pugi::xml_node parent, } } else { VTR_ASSERT(BI_DIRECTIONAL == Segs[i].directionality); - SubElem = get_single_child(Node, "wire_switch", loc_data); + SubElem = get_single_child(node, "wire_switch", loc_data); tmp = get_attribute(SubElem, "name", loc_data).value(); /* Match names */ @@ -4066,7 +4066,7 @@ static std::vector process_segments(pugi::xml_node parent, vtr::string_fmt("'%s' is not a valid wire_switch name.\n", tmp).c_str()); } Segs[i].arch_wire_switch = switch_idx; - SubElem = get_single_child(Node, "opin_switch", loc_data); + SubElem = get_single_child(node, "opin_switch", loc_data); tmp = get_attribute(SubElem, "name", loc_data).value(); /* Match names */ @@ -4083,7 +4083,7 @@ static std::vector process_segments(pugi::xml_node parent, for (int j = 0; j < length; ++j) { Segs[i].cb[j] = true; } - SubElem = get_single_child(Node, "cb", loc_data, ReqOpt::OPTIONAL); + SubElem = get_single_child(node, "cb", loc_data, ReqOpt::OPTIONAL); if (SubElem) { process_cb_sb(SubElem, Segs[i].cb, loc_data); } @@ -4093,7 +4093,7 @@ static std::vector process_segments(pugi::xml_node parent, for (int j = 0; j < (length + 1); ++j) { Segs[i].sb[j] = true; } - SubElem = get_single_child(Node, "sb", loc_data, ReqOpt::OPTIONAL); + SubElem = get_single_child(node, "sb", loc_data, ReqOpt::OPTIONAL); if (SubElem) { process_cb_sb(SubElem, Segs[i].sb, loc_data); } @@ -4101,7 +4101,7 @@ static std::vector process_segments(pugi::xml_node parent, // Setup the bend list if they give one, otherwise use default if (length > 1) { Segs[i].is_bend = false; - SubElem = get_single_child(Node, "bend", loc_data, ReqOpt::OPTIONAL); + SubElem = get_single_child(node, "bend", loc_data, ReqOpt::OPTIONAL); if (SubElem) { process_bend(SubElem, Segs[i], (length - 1), loc_data); } @@ -4109,35 +4109,35 @@ static std::vector process_segments(pugi::xml_node parent, // Store the index of this segment in Segs vector Segs[i].seg_index = i; - // Get next Node - Node = Node.next_sibling(Node.name()); + // Get next node + node = node.next_sibling(node.name()); } // We need at least one type of segment that applies to each of x- and y-directed wiring. if (!x_axis_seg_found || !y_axis_seg_found) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("At least one segment per-axis needs to get specified if no segments with non-specified (default) axis attribute exist.").c_str()); } if (num_layers > 1 && !z_axis_seg_found) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("At least one segment along Z axis needs to get specified if for 3D architectures.").c_str()); } return Segs; } -static void process_bend(pugi::xml_node Node, t_segment_inf& segment, const int len, const pugiutil::loc_data& loc_data) { +static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int len, const pugiutil::loc_data& loc_data) { std::vector& list = segment.bend; std::vector& part_len = segment.part_len; bool& is_bend = segment.is_bend; - std::string tmp = std::string(get_attribute(Node, "type", loc_data).value()); + std::string tmp = std::string(get_attribute(node, "type", loc_data).value()); if (tmp == "pattern") { int i = 0; /* Get the content string */ - std::string content = std::string(Node.child_value()); + std::string content = std::string(node.child_value()); for (char c : content) { switch (c) { case ' ': @@ -4156,23 +4156,23 @@ static void process_bend(pugi::xml_node Node, t_segment_inf& segment, const int is_bend = true; break; case 'B': - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), "B pattern is not supported in current version\n"); break; default: - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), "Invalid character %c in CB or SB depopulation list.\n", c); } } if (list.size() != size_t(len)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), "Wrong length of bend list (%d). Expect %d symbols.\n", i, len); } } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), "'%s' is not a valid type for specifying bend list.\n", tmp.c_str()); } @@ -4237,7 +4237,7 @@ static void calculate_custom_sb_locations(const pugiutil::loc_data& loc_data, * See vpr/SRC/route/build_switchblocks.c for a detailed description of this * switch block format */ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data) { - pugi::xml_node Node; + pugi::xml_node node; pugi::xml_node SubElem; const char* tmp; @@ -4254,32 +4254,32 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug } /* read-in all switchblock data */ - Node = get_first_child(Parent, "switchblock", loc_data); + node = get_first_child(Parent, "switchblock", loc_data); for (int i_sb = 0; i_sb < num_switchblocks; i_sb++) { /* use a temp variable which will be assigned to switchblocks later */ t_switchblock_inf sb; /* get name */ - tmp = get_attribute(Node, "name", loc_data).as_string(nullptr); + tmp = get_attribute(node, "name", loc_data).as_string(nullptr); if (tmp) { sb.name = tmp; } /* get type */ - tmp = get_attribute(Node, "type", loc_data).as_string(nullptr); + tmp = get_attribute(node, "type", loc_data).as_string(nullptr); if (tmp) { if (0 == strcmp(tmp, "bidir")) { sb.directionality = BI_DIRECTIONAL; } else if (0 == strcmp(tmp, "unidir")) { sb.directionality = UNI_DIRECTIONAL; } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Unsopported switchblock type: %s\n", tmp).c_str()); } } // get the switchblock location - SubElem = get_single_child(Node, "switchblock_location", loc_data); + SubElem = get_single_child(node, "switchblock_location", loc_data); tmp = get_attribute(SubElem, "type", loc_data).as_string(nullptr); if (tmp) { auto sb_location_iter = SB_LOCATION_STRING_MAP.find(tmp); @@ -4327,10 +4327,10 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug } // get switchblock permutation functions - SubElem = get_first_child(Node, "switchfuncs", loc_data); + SubElem = get_first_child(node, "switchfuncs", loc_data); read_sb_switchfuncs(SubElem, sb, loc_data); - read_sb_wireconns(arch->switches, Node, sb, loc_data); + read_sb_wireconns(arch->switches, node, sb, loc_data); // run error checks on switch blocks check_switchblock(sb, arch); @@ -4338,22 +4338,22 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug // assign the sb to the switchblocks vector arch->switchblocks.push_back(sb); - Node = Node.next_sibling(Node.name()); + node = node.next_sibling(node.name()); } } -static void process_cb_sb(pugi::xml_node Node, std::vector& list, const pugiutil::loc_data& loc_data) { +static void process_cb_sb(pugi::xml_node node, std::vector& list, const pugiutil::loc_data& loc_data) { const char* tmp = nullptr; int len = list.size(); // Check the type. We only support 'pattern' for now. // Should add frac back eventually. - tmp = get_attribute(Node, "type", loc_data).value(); + tmp = get_attribute(node, "type", loc_data).value(); if (0 == strcmp(tmp, "pattern")) { int i = 0; // Get the content string - tmp = Node.child_value(); + tmp = node.child_value(); while (*tmp) { switch (*tmp) { case ' ': @@ -4363,7 +4363,7 @@ static void process_cb_sb(pugi::xml_node Node, std::vector& list, const pu case 'T': case '1': if (i >= len) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("CB or SB depopulation is too long (%d). It should be %d symbols for CBs and %d symbols for SBs.\n", i, len - 1, len) .c_str()); @@ -4374,7 +4374,7 @@ static void process_cb_sb(pugi::xml_node Node, std::vector& list, const pu case 'F': case '0': if (i >= len) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("CB or SB depopulation is too long (%d). It should be %d symbols for CBs and %d symbols for SBs.\n", i, len - 1, len) .c_str()); @@ -4383,7 +4383,7 @@ static void process_cb_sb(pugi::xml_node Node, std::vector& list, const pu ++i; break; default: - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Invalid character %c in CB or SB depopulation list.\n", *tmp) .c_str()); @@ -4391,7 +4391,7 @@ static void process_cb_sb(pugi::xml_node Node, std::vector& list, const pu ++tmp; } if (i < len) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("CB or SB depopulation is too short (%d). It should be %d symbols for CBs and %d symbols for SBs.\n", i, len - 1, len) .c_str()); @@ -4399,7 +4399,7 @@ static void process_cb_sb(pugi::xml_node Node, std::vector& list, const pu } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("'%s' is not a valid type for specifying cb and sb depopulation.\n", tmp).c_str()); } } @@ -4411,7 +4411,7 @@ static std::vector process_switches(pugi::xml_node Parent, const char* switch_name; ReqOpt TIMING_ENABLE_REQD = BoolToReqOpt(timing_enabled); - pugi::xml_node Node; + pugi::xml_node node; /* Count the children and check they are switches */ int n_switches = count_children(Parent, "switch", loc_data); @@ -4423,26 +4423,26 @@ static std::vector process_switches(pugi::xml_node Parent, } /* Load the switches. */ - Node = get_first_child(Parent, "switch", loc_data); + node = get_first_child(Parent, "switch", loc_data); for (int i = 0; i < n_switches; ++i) { t_arch_switch_inf& arch_switch = switches[i]; - switch_name = get_attribute(Node, "name", loc_data).value(); + switch_name = get_attribute(node, "name", loc_data).value(); /* Check if the switch has conflicts with any reserved names */ if (0 == strcmp(switch_name, VPR_DELAYLESS_SWITCH_NAME)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Switch name '%s' is a reserved name for VPR internal usage! Please use another name.\n", switch_name) .c_str()); } - type_name = get_attribute(Node, "type", loc_data).value(); + type_name = get_attribute(node, "type", loc_data).value(); /* Check for switch name collisions */ for (int j = 0; j < i; ++j) { if (0 == strcmp(switches[j].name.c_str(), switch_name)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Two switches with the same name '%s' were found.\n", switch_name) .c_str()); @@ -4457,30 +4457,30 @@ static std::vector process_switches(pugi::xml_node Parent, e_switch_type type = e_switch_type::MUX; if (0 == strcmp(type_name, "mux")) { type = e_switch_type::MUX; - expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data); + expect_only_attributes(node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data); } else if (0 == strcmp(type_name, "tristate")) { type = e_switch_type::TRISTATE; - expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data); + expect_only_attributes(node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data); } else if (0 == strcmp(type_name, "buffer")) { type = e_switch_type::BUFFER; - expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data); + expect_only_attributes(node, {"type", "name", "R", "Cin", "Cout", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data); } else if (0 == strcmp(type_name, "pass_gate")) { type = e_switch_type::PASS_GATE; - expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type '"s + type_name + "'"s, loc_data); + expect_only_attributes(node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type '"s + type_name + "'"s, loc_data); } else if (0 == strcmp(type_name, "short")) { type = e_switch_type::SHORT; - expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type "s + type_name + "'"s, loc_data); + expect_only_attributes(node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type "s + type_name + "'"s, loc_data); } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Invalid switch type '%s'.\n", type_name).c_str()); } arch_switch.set_type(type); - arch_switch.R = get_attribute(Node, "R", loc_data, TIMING_ENABLE_REQD).as_float(0); + arch_switch.R = get_attribute(node, "R", loc_data, TIMING_ENABLE_REQD).as_float(0); ReqOpt COUT_REQD = TIMING_ENABLE_REQD; ReqOpt CIN_REQD = TIMING_ENABLE_REQD; @@ -4493,13 +4493,13 @@ static std::vector process_switches(pugi::xml_node Parent, CIN_REQD = ReqOpt::OPTIONAL; COUT_REQD = ReqOpt::OPTIONAL; } - arch_switch.Cin = get_attribute(Node, "Cin", loc_data, CIN_REQD).as_float(0); - arch_switch.Cout = get_attribute(Node, "Cout", loc_data, COUT_REQD).as_float(0); - arch_switch.Cinternal = get_attribute(Node, "Cinternal", loc_data, CINTERNAL_REQD).as_float(0); + arch_switch.Cin = get_attribute(node, "Cin", loc_data, CIN_REQD).as_float(0); + arch_switch.Cout = get_attribute(node, "Cout", loc_data, COUT_REQD).as_float(0); + arch_switch.Cinternal = get_attribute(node, "Cinternal", loc_data, CINTERNAL_REQD).as_float(0); if (arch_switch.type() == e_switch_type::MUX) { //Only muxes have mux transistors - arch_switch.mux_trans_size = get_attribute(Node, "mux_trans_size", loc_data, ReqOpt::OPTIONAL).as_float(1); + arch_switch.mux_trans_size = get_attribute(node, "mux_trans_size", loc_data, ReqOpt::OPTIONAL).as_float(1); } else { arch_switch.mux_trans_size = 0.; } @@ -4512,7 +4512,7 @@ static std::vector process_switches(pugi::xml_node Parent, arch_switch.power_buffer_type = POWER_BUFFER_TYPE_ABSOLUTE_SIZE; arch_switch.power_buffer_size = 0.; } else { - auto buf_size_attrib = get_attribute(Node, "buf_size", loc_data, ReqOpt::OPTIONAL); + auto buf_size_attrib = get_attribute(node, "buf_size", loc_data, ReqOpt::OPTIONAL); if (!buf_size_attrib || buf_size_attrib.as_string() == std::string("auto")) { arch_switch.buf_size_type = e_buffer_size::AUTO; arch_switch.buf_size = 0.; @@ -4521,7 +4521,7 @@ static std::vector process_switches(pugi::xml_node Parent, arch_switch.buf_size = buf_size_attrib.as_float(); } - auto power_buf_size = get_attribute(Node, "power_buf_size", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + auto power_buf_size = get_attribute(node, "power_buf_size", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (power_buf_size == nullptr) { arch_switch.power_buffer_type = POWER_BUFFER_TYPE_AUTO; } else if (strcmp(power_buf_size, "auto") == 0) { @@ -4535,10 +4535,10 @@ static std::vector process_switches(pugi::xml_node Parent, } //Load the Tdel (which may be specified with sub-tags) - process_switch_tdel(Node, timing_enabled, arch_switch, loc_data); + process_switch_tdel(node, timing_enabled, arch_switch, loc_data); /* Get next switch element */ - Node = Node.next_sibling(Node.name()); + node = node.next_sibling(node.name()); } return switches; @@ -4553,24 +4553,24 @@ static std::vector process_switches(pugi::xml_node Parent, * * are specified as children of the switch node. In this case, Tdel * is not included as a property of the switch node (first way). */ -static void process_switch_tdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data) { +static void process_switch_tdel(pugi::xml_node node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data) { /* check if switch node has the Tdel property */ bool has_Tdel_prop = false; - float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); + float Tdel_prop_value = get_attribute(node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); if (Tdel_prop_value != ARCH_FPGA_UNDEFINED_VAL) { has_Tdel_prop = true; } /* check if switch node has Tdel children */ bool has_Tdel_children = false; - int num_Tdel_children = count_children(Node, "Tdel", loc_data, ReqOpt::OPTIONAL); + int num_Tdel_children = count_children(node, "Tdel", loc_data, ReqOpt::OPTIONAL); if (num_Tdel_children != 0) { has_Tdel_children = true; } /* delay should not be specified as a Tdel property AND a Tdel child */ if (has_Tdel_prop && has_Tdel_children) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Switch delay should be specified as EITHER a Tdel property OR as a child of the switch node, not both").c_str()); } @@ -4582,7 +4582,7 @@ static void process_switch_tdel(pugi::xml_node Node, const bool timing_enabled, /* Delay specified as a function of switch fan-in. * Go through each Tdel child, read-in num_inputs and the delay value. * Insert this info into the switch delay map */ - pugi::xml_node Tdel_child = get_first_child(Node, "Tdel", loc_data); + pugi::xml_node Tdel_child = get_first_child(node, "Tdel", loc_data); std::set seen_fanins; for (int ichild = 0; ichild < num_Tdel_children; ichild++) { int num_inputs = get_attribute(Tdel_child, "num_inputs", loc_data).as_int(0); @@ -4600,7 +4600,7 @@ static void process_switch_tdel(pugi::xml_node Node, const bool timing_enabled, } else { /* No delay info specified for switch */ if (timing_enabled) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Switch should contain intrinsic delay information if timing is enabled").c_str()); } else { /* set a default value */ @@ -4618,15 +4618,15 @@ static std::vector process_directs(pugi::xml_node Parent, std::vector directs(num_directs); /* Load the directs. */ - pugi::xml_node Node = get_first_child(Parent, "direct", loc_data); + pugi::xml_node node = get_first_child(Parent, "direct", loc_data); for (int i = 0; i < num_directs; ++i) { - expect_only_attributes(Node, {"name", "from_pin", "to_pin", "x_offset", "y_offset", "z_offset", "switch_name", "from_side", "to_side"}, loc_data); + expect_only_attributes(node, {"name", "from_pin", "to_pin", "x_offset", "y_offset", "z_offset", "switch_name", "from_side", "to_side"}, loc_data); - const char* direct_name = get_attribute(Node, "name", loc_data).value(); + const char* direct_name = get_attribute(node, "name", loc_data).value(); /* Check for direct name collisions */ for (int j = 0; j < i; ++j) { if (directs[j].name == direct_name) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Two directs with the same name '%s' were found.\n", direct_name) .c_str()); @@ -4635,12 +4635,12 @@ static std::vector process_directs(pugi::xml_node Parent, directs[i].name = direct_name; /* Figure out the source pin and sink pin name */ - const char* from_pin_name = get_attribute(Node, "from_pin", loc_data).value(); - const char* to_pin_name = get_attribute(Node, "to_pin", loc_data).value(); + const char* from_pin_name = get_attribute(node, "from_pin", loc_data).value(); + const char* to_pin_name = get_attribute(node, "to_pin", loc_data).value(); /* Check that to_pin and the from_pin are not the same */ if (0 == strcmp(to_pin_name, from_pin_name)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("The source pin and sink pin are the same: %s.\n", to_pin_name) .c_str()); @@ -4648,22 +4648,22 @@ static std::vector process_directs(pugi::xml_node Parent, directs[i].from_pin = from_pin_name; directs[i].to_pin = to_pin_name; - directs[i].x_offset = get_attribute(Node, "x_offset", loc_data).as_int(0); - directs[i].y_offset = get_attribute(Node, "y_offset", loc_data).as_int(0); - directs[i].sub_tile_offset = get_attribute(Node, "z_offset", loc_data).as_int(0); + directs[i].x_offset = get_attribute(node, "x_offset", loc_data).as_int(0); + directs[i].y_offset = get_attribute(node, "y_offset", loc_data).as_int(0); + directs[i].sub_tile_offset = get_attribute(node, "z_offset", loc_data).as_int(0); - std::string from_side_str = get_attribute(Node, "from_side", loc_data, ReqOpt::OPTIONAL).value(); + std::string from_side_str = get_attribute(node, "from_side", loc_data, ReqOpt::OPTIONAL).value(); directs[i].from_side = string_to_side(from_side_str); - std::string to_side_str = get_attribute(Node, "to_side", loc_data, ReqOpt::OPTIONAL).value(); + std::string to_side_str = get_attribute(node, "to_side", loc_data, ReqOpt::OPTIONAL).value(); directs[i].to_side = string_to_side(to_side_str); //Set the optional switch type - const char* switch_name = get_attribute(Node, "switch_name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + const char* switch_name = get_attribute(node, "switch_name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (switch_name != nullptr) { //Look-up the user defined switch int switch_idx = find_switch_by_name(switches, switch_name); if (switch_idx < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Could not find switch named '%s' in switch list.\n", switch_name) .c_str()); @@ -4677,11 +4677,11 @@ static std::vector process_directs(pugi::xml_node Parent, directs[i].switch_type = -1; } - directs[i].line = loc_data.line(Node); + directs[i].line = loc_data.line(node); /* Should I check that the direct chain offset is not greater than the chip? How? */ /* Get next direct element */ - Node = Node.next_sibling(Node.name()); + node = node.next_sibling(node.name()); } return directs; @@ -5016,7 +5016,7 @@ static void process_power(pugi::xml_node parent, /* Get the clock architecture */ static void process_clocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data) { - pugi::xml_node Node; + pugi::xml_node node; const char* tmp; int num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); @@ -5024,9 +5024,9 @@ static void process_clocks(pugi::xml_node Parent, std::vector& clocks.resize(num_global_clocks, t_clock_network()); /* Load the clock info. */ - Node = get_first_child(Parent, "clock", loc_data); + node = get_first_child(Parent, "clock", loc_data); for (int i = 0; i < num_global_clocks; ++i) { - tmp = get_attribute(Node, "buffer_size", loc_data).value(); + tmp = get_attribute(node, "buffer_size", loc_data).value(); if (strcmp(tmp, "auto") == 0) { clocks[i].autosize_buffer = true; } else { @@ -5034,10 +5034,10 @@ static void process_clocks(pugi::xml_node Parent, std::vector& clocks[i].buffer_size = (float)atof(tmp); } - clocks[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0); + clocks[i].C_wire = get_attribute(node, "C_wire", loc_data).as_float(0); /* get the next clock item */ - Node = Node.next_sibling(Node.name()); + node = node.next_sibling(node.name()); } } From 307d184c49b8a8f5044348ea24ca106ba6aacb4f Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 13:44:03 -0400 Subject: [PATCH 02/14] rename SubTile and CurSubTile to sub_tile and cur_sub_tile --- libs/libarchfpga/src/read_xml_arch_file.cpp | 130 ++++++++++---------- 1 file changed, 65 insertions(+), 65 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 5c2df12772..d5c41b4886 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -155,7 +155,7 @@ static void process_tile_props(pugi::xml_node node, const pugiutil::loc_data& loc_data); static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, const pugiutil::loc_data& loc_data); static void process_tile_port(pugi::xml_node node, @@ -163,24 +163,24 @@ static void process_tile_port(pugi::xml_node node, const pugiutil::loc_data& loc_data); static void process_tile_equivalent_sites(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_physical_tile_type* PhysicalTileType, std::vector& LogicalBlockTypes, const pugiutil::loc_data& loc_data); static void process_equivalent_site_direct_connection(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, const pugiutil::loc_data& loc_data); static void process_equivalent_site_custom_connection(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, const std::string& site_name, const pugiutil::loc_data& loc_data); static void process_pin_locations(pugi::xml_node Locations, t_physical_tile_type* PhysicalTileType, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_pin_locs* pin_locs, const pugiutil::loc_data& loc_data, const int num_of_avail_layer); @@ -265,7 +265,7 @@ static void process_mode(pugi::xml_node Parent, static void process_fc_values(pugi::xml_node node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data); static void process_fc(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_pin_counts pin_counts, std::vector& segments, const t_default_fc_spec& arch_def_fc, @@ -2021,7 +2021,7 @@ static void process_fc_values(pugi::xml_node node, t_default_fc_spec& spec, cons * the appropriate fields of type. */ static void process_fc(pugi::xml_node node, t_physical_tile_type* PhysicalTileType, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_pin_counts pin_counts, std::vector& segments, const t_default_fc_spec& arch_def_fc, @@ -2048,12 +2048,12 @@ static void process_fc(pugi::xml_node node, /* Go through all the port/segment combinations and create the (potentially * overriden) pin/seg Fc specifications */ for (size_t iseg = 0; iseg < segments.size(); ++iseg) { - for (int icapacity = 0; icapacity < SubTile->capacity.total(); ++icapacity) { + for (int icapacity = 0; icapacity < sub_tile->capacity.total(); ++icapacity) { //If capacity > 0, we need t offset the block index by the number of pins per instance //this ensures that all pins have an Fc specification int iblk_pin = icapacity * pin_counts.total(); - for (const auto& port : SubTile->ports) { + for (const auto& port : sub_tile->ports) { t_fc_specification fc_spec; fc_spec.seg_index = iseg; @@ -2116,7 +2116,7 @@ static void process_fc(pugi::xml_node node, for (int iport_pin = 0; iport_pin < port.num_pins; ++iport_pin) { //XXX: this assumes that iterating through the tile ports // in order yields the block pin order - int true_physical_blk_pin = SubTile->sub_tile_to_tile_pin_indices[iblk_pin]; + int true_physical_blk_pin = sub_tile->sub_tile_to_tile_pin_indices[iblk_pin]; fc_spec.pins.push_back(true_physical_blk_pin); ++iblk_pin; } @@ -3166,7 +3166,7 @@ static void process_tile_props(pugi::xml_node node, } static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, const pugiutil::loc_data& loc_data) { pugi::xml_node Cur; @@ -3197,12 +3197,12 @@ static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, if (!subtile_success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), vtr::string_fmt("Duplicate port names in subtile '%s': port '%s'\n", - SubTile->name.c_str(), port.name) + sub_tile->name.c_str(), port.name) .c_str()); } //Push port - SubTile->ports.push_back(port); + sub_tile->ports.push_back(port); /* get next iteration */ port_index++; @@ -3218,7 +3218,7 @@ static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, t_pin_counts pin_counts; /* Count stats on the number of each type of pin */ - for (const auto& port : SubTile->ports) { + for (const auto& port : sub_tile->ports) { if (port.type == IN_PORT && !port.is_clock) { pin_counts.input += port.num_pins; } else if (port.type == OUT_PORT) { @@ -3301,7 +3301,7 @@ static void process_tile_port(pugi::xml_node node, } static void process_tile_equivalent_sites(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_physical_tile_type* PhysicalTileType, std::vector& LogicalBlockTypes, const pugiutil::loc_data& loc_data) { @@ -3311,7 +3311,7 @@ static void process_tile_equivalent_sites(pugi::xml_node Parent, if (count_children(Parent, "site", loc_data) < 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - vtr::string_fmt("There are no sites corresponding to this tile: %s.\n", SubTile->name.c_str()).c_str()); + vtr::string_fmt("There are no sites corresponding to this tile: %s.\n", sub_tile->name.c_str()).c_str()); } CurSite = Parent.first_child(); @@ -3328,15 +3328,15 @@ static void process_tile_equivalent_sites(pugi::xml_node Parent, if (0 == strcmp(pin_mapping, "custom")) { // Pin mapping between Tile and Pb Type is user-defined - process_equivalent_site_custom_connection(CurSite, SubTile, PhysicalTileType, LogicalBlockType, Prop, loc_data); + process_equivalent_site_custom_connection(CurSite, sub_tile, PhysicalTileType, LogicalBlockType, Prop, loc_data); } else if (0 == strcmp(pin_mapping, "direct")) { - process_equivalent_site_direct_connection(CurSite, SubTile, PhysicalTileType, LogicalBlockType, loc_data); + process_equivalent_site_direct_connection(CurSite, sub_tile, PhysicalTileType, LogicalBlockType, loc_data); } if (0 == strcmp(LogicalBlockType->pb_type->name, Prop.c_str())) { - SubTile->equivalent_sites.push_back(LogicalBlockType); + sub_tile->equivalent_sites.push_back(LogicalBlockType); - check_port_direct_mappings(PhysicalTileType, SubTile, LogicalBlockType); + check_port_direct_mappings(PhysicalTileType, sub_tile, LogicalBlockType); } CurSite = CurSite.next_sibling(CurSite.name()); @@ -3344,17 +3344,17 @@ static void process_tile_equivalent_sites(pugi::xml_node Parent, } static void process_equivalent_site_direct_connection(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, const pugiutil::loc_data& loc_data) { - int num_pins = (int)SubTile->sub_tile_to_tile_pin_indices.size() / SubTile->capacity.total(); + int num_pins = (int)sub_tile->sub_tile_to_tile_pin_indices.size() / sub_tile->capacity.total(); if (num_pins != LogicalBlockType->pb_type->num_pins) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), vtr::string_fmt("Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, - SubTile->name.c_str()) + sub_tile->name.c_str()) .c_str()); } @@ -3367,11 +3367,11 @@ static void process_equivalent_site_direct_connection(pugi::xml_node Parent, directs_map.insert(logical_pin, physical_pin); } - PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][SubTile->index] = directs_map; + PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][sub_tile->index] = directs_map; } static void process_equivalent_site_custom_connection(pugi::xml_node Parent, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_physical_tile_type* PhysicalTileType, t_logical_block_type* LogicalBlockType, const std::string& site_name, @@ -3383,7 +3383,7 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, if (count_children(Parent, "direct", loc_data) < 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), vtr::string_fmt("There are no direct pin mappings between site %s and tile %s.\n", - site_name.c_str(), SubTile->name.c_str()) + site_name.c_str(), sub_tile->name.c_str()) .c_str()); } @@ -3403,7 +3403,7 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, // `to` attribute is relative to the logical block pins to = std::string(get_attribute(CurDirect, "to", loc_data).value()); - auto from_pins = process_pin_string(CurDirect, SubTile, from.c_str(), loc_data); + auto from_pins = process_pin_string(CurDirect, sub_tile, from.c_str(), loc_data); auto to_pins = process_pin_string(CurDirect, LogicalBlockType, to.c_str(), loc_data); // Checking that the number of pins is exactly the same @@ -3411,7 +3411,7 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), vtr::string_fmt("The number of pins specified in the direct pin mapping is " "not equivalent for Physical Tile %s and Logical Block %s.\n", - SubTile->name.c_str(), LogicalBlockType->name.c_str()) + sub_tile->name.c_str(), LogicalBlockType->name.c_str()) .c_str()); } @@ -3425,7 +3425,7 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), vtr::string_fmt("Duplicate logical pin (%d) to physical pin (%d) mappings found for " "Physical Tile %s and Logical Block %s.\n", - logical_pin.pin, physical_pin.pin, SubTile->name.c_str(), LogicalBlockType->name.c_str()) + logical_pin.pin, physical_pin.pin, sub_tile->name.c_str(), LogicalBlockType->name.c_str()) .c_str()); } } @@ -3433,12 +3433,12 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, CurDirect = CurDirect.next_sibling(CurDirect.name()); } - PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][SubTile->index] = directs_map; + PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][sub_tile->index] = directs_map; } static void process_pin_locations(pugi::xml_node Locations, t_physical_tile_type* PhysicalTileType, - t_sub_tile* SubTile, + t_sub_tile* sub_tile, t_pin_locs* pin_locs, const pugiutil::loc_data& loc_data, const int num_of_avail_layer) { @@ -3472,7 +3472,7 @@ static void process_pin_locations(pugi::xml_node Locations, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Sub Tile %s has a different pin location pattern (%s) with respect " "to the sibling sub tiles", - SubTile->name.c_str(), Prop) + sub_tile->name.c_str(), Prop) .c_str()); } } else { @@ -3480,7 +3480,7 @@ static void process_pin_locations(pugi::xml_node Locations, pin_locs->set_distribution(); } - const int sub_tile_index = SubTile->index; + const int sub_tile_index = sub_tile->index; /* Load the pin locations */ if (distribution == e_pin_location_distr::CUSTOM) { @@ -3571,7 +3571,7 @@ static void process_pin_locations(pugi::xml_node Locations, //A pin specification should contain only the block name, and not any instance count information //A pin specification may contain instance count, but should be in the range of capacity int inst_lsb = 0; - int inst_msb = SubTile->capacity.total() - 1; + int inst_msb = sub_tile->capacity.total() - 1; if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) { /* Extract range numbers */ inst_lsb = inst_port.instance_low_index(); @@ -3580,19 +3580,19 @@ static void process_pin_locations(pugi::xml_node Locations, std::swap(inst_lsb, inst_msb); } /* Check if we have a valid range */ - if (inst_lsb < 0 || inst_msb > SubTile->capacity.total() - 1) { + if (inst_lsb < 0 || inst_msb > sub_tile->capacity.total() - 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Pin location specification '%s' contain an out-of-range instance. Expect [%d:%d]", - token.c_str(), 0, SubTile->capacity.total() - 1) + token.c_str(), 0, sub_tile->capacity.total() - 1) .c_str()); } } //Check that the block name matches - if (inst_port.instance_name() != SubTile->name) { + if (inst_port.instance_name() != sub_tile->name) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Mismatched sub tile name in pin location specification (expected '%s' was '%s')", - SubTile->name.c_str(), inst_port.instance_name().c_str()) + sub_tile->name.c_str(), inst_port.instance_name().c_str()) .c_str()); } @@ -3604,7 +3604,7 @@ static void process_pin_locations(pugi::xml_node Locations, //Find the matching pb type to get the total number of pins const t_physical_tile_port* port = nullptr; - for (const auto& tmp_port : SubTile->ports) { + for (const auto& tmp_port : sub_tile->ports) { if (tmp_port.name == inst_port.port_name()) { port = &tmp_port; break; @@ -3617,14 +3617,14 @@ static void process_pin_locations(pugi::xml_node Locations, } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Failed to find port named '%s' on block '%s'", - inst_port.port_name().c_str(), SubTile->name.c_str()) + inst_port.port_name().c_str(), sub_tile->name.c_str()) .c_str()); } } VTR_ASSERT(pin_low_idx >= 0); VTR_ASSERT(pin_high_idx >= 0); - for (int iinst = inst_lsb + SubTile->capacity.low; iinst <= inst_msb + SubTile->capacity.low; ++iinst) { + for (int iinst = inst_lsb + sub_tile->capacity.low; iinst <= inst_msb + sub_tile->capacity.low; ++iinst) { for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { //Record that the pin has it's location specified port_pins_with_specified_locations[iinst][inst_port.port_name()].insert(ipin); @@ -3637,14 +3637,14 @@ static void process_pin_locations(pugi::xml_node Locations, } //Check for any pins missing location specs - for (int iinst = SubTile->capacity.low; iinst < SubTile->capacity.high; ++iinst) { - for (const t_physical_tile_port& port : SubTile->ports) { + for (int iinst = sub_tile->capacity.low; iinst < sub_tile->capacity.high; ++iinst) { + for (const t_physical_tile_port& port : sub_tile->ports) { for (int ipin = 0; ipin < port.num_pins; ++ipin) { if (!port_pins_with_specified_locations[iinst][port.name].count(ipin)) { //Missing archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", - SubTile->name.c_str(), iinst, port.name, ipin) + sub_tile->name.c_str(), iinst, port.name, ipin) .c_str()); } } @@ -3663,7 +3663,7 @@ static void process_sub_tiles(pugi::xml_node node, const t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data, const int num_of_avail_layer) { - pugi::xml_node CurSubTile; + pugi::xml_node cur_sub_tile; pugi::xml_node Cur; unsigned long int num_sub_tiles = count_children(node, "sub_tile", loc_data); @@ -3688,17 +3688,17 @@ static void process_sub_tiles(pugi::xml_node node, // used to assign indices to subtiles int subtile_index = 0; - CurSubTile = get_first_child(node, "sub_tile", loc_data); + cur_sub_tile = get_first_child(node, "sub_tile", loc_data); - while (CurSubTile) { - t_sub_tile SubTile; + while (cur_sub_tile) { + t_sub_tile sub_tile; - SubTile.index = subtile_index; + sub_tile.index = subtile_index; - expect_only_attributes(CurSubTile, {"name", "capacity"}, loc_data); + expect_only_attributes(cur_sub_tile, {"name", "capacity"}, loc_data); /* Load type name */ - const char* name = get_attribute(CurSubTile, "name", loc_data).value(); + const char* name = get_attribute(cur_sub_tile, "name", loc_data).value(); //Check Sub Tile name duplicates auto [_, success] = sub_tile_names.insert(name); @@ -3709,24 +3709,24 @@ static void process_sub_tiles(pugi::xml_node node, .c_str()); } - SubTile.name = name; + sub_tile.name = name; /* Load properties */ - int capacity = get_attribute(CurSubTile, "capacity", loc_data, ReqOpt::OPTIONAL).as_int(1); - SubTile.capacity.set(PhysicalTileType->capacity, PhysicalTileType->capacity + capacity - 1); + int capacity = get_attribute(cur_sub_tile, "capacity", loc_data, ReqOpt::OPTIONAL).as_int(1); + sub_tile.capacity.set(PhysicalTileType->capacity, PhysicalTileType->capacity + capacity - 1); PhysicalTileType->capacity += capacity; /* Process sub tile port definitions */ - const auto pin_counts = process_sub_tile_ports(CurSubTile, &SubTile, loc_data); + const auto pin_counts = process_sub_tile_ports(cur_sub_tile, &sub_tile, loc_data); /* Map Sub Tile physical pins with the Physical Tile Type physical pins. * This takes into account the capacity of each sub tiles to add the correct offset. */ for (int ipin = 0; ipin < capacity * pin_counts.total(); ipin++) { - SubTile.sub_tile_to_tile_pin_indices.push_back(PhysicalTileType->num_pins + ipin); + sub_tile.sub_tile_to_tile_pin_indices.push_back(PhysicalTileType->num_pins + ipin); } - SubTile.num_phy_pins = pin_counts.total() * capacity; + sub_tile.num_phy_pins = pin_counts.total() * capacity; /* Assign pin counts to the Physical Tile Type */ PhysicalTileType->num_input_pins += capacity * pin_counts.input; @@ -3739,22 +3739,22 @@ static void process_sub_tiles(pugi::xml_node node, PhysicalTileType->num_receivers += capacity * pin_counts.input; PhysicalTileType->num_drivers += capacity * pin_counts.output; - Cur = get_single_child(CurSubTile, "pinlocations", loc_data, ReqOpt::OPTIONAL); - process_pin_locations(Cur, PhysicalTileType, &SubTile, &pin_locs, loc_data, num_of_avail_layer); + Cur = get_single_child(cur_sub_tile, "pinlocations", loc_data, ReqOpt::OPTIONAL); + process_pin_locations(Cur, PhysicalTileType, &sub_tile, &pin_locs, loc_data, num_of_avail_layer); /* Load Fc */ - Cur = get_single_child(CurSubTile, "fc", loc_data, ReqOpt::OPTIONAL); - process_fc(Cur, PhysicalTileType, &SubTile, pin_counts, segments, arch_def_fc, loc_data); + Cur = get_single_child(cur_sub_tile, "fc", loc_data, ReqOpt::OPTIONAL); + process_fc(Cur, PhysicalTileType, &sub_tile, pin_counts, segments, arch_def_fc, loc_data); //Load equivalent sites information - Cur = get_single_child(CurSubTile, "equivalent_sites", loc_data, ReqOpt::REQUIRED); - process_tile_equivalent_sites(Cur, &SubTile, PhysicalTileType, LogicalBlockTypes, loc_data); + Cur = get_single_child(cur_sub_tile, "equivalent_sites", loc_data, ReqOpt::REQUIRED); + process_tile_equivalent_sites(Cur, &sub_tile, PhysicalTileType, LogicalBlockTypes, loc_data); - PhysicalTileType->sub_tiles.push_back(SubTile); + PhysicalTileType->sub_tiles.push_back(sub_tile); subtile_index++; - CurSubTile = CurSubTile.next_sibling(CurSubTile.name()); + cur_sub_tile = cur_sub_tile.next_sibling(cur_sub_tile.name()); } // Initialize pinloc data structure. From d6128b173cb3afdf5d59cc7799f7fd26b5f2f486 Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 13:48:43 -0400 Subject: [PATCH 03/14] Next ---> next --- libs/libarchfpga/src/read_xml_arch_file.cpp | 112 ++++++++++---------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index d5c41b4886..319df1e394 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -401,7 +401,7 @@ void xml_read_arch(const char* ArchFile, t_arch* arch, std::vector& PhysicalTileTypes, std::vector& LogicalBlockTypes) { - pugi::xml_node Next; + pugi::xml_node next; ReqOpt POWER_REQD, SWITCHBLOCKLIST_REQD; if (!vtr::check_file_name_extension(ArchFile, ".xml")) { @@ -437,79 +437,79 @@ void xml_read_arch(const char* ArchFile, } #endif - /* Process models */ - Next = get_single_child(architecture, "models", loc_data); - process_models(Next, arch, loc_data); + // Process models + next = get_single_child(architecture, "models", loc_data); + process_models(next, arch, loc_data); - /* Process layout */ + // Process layout int num_of_avail_layers = 0; - Next = get_single_child(architecture, "layout", loc_data); - process_layout(Next, arch, loc_data, num_of_avail_layers); + next = get_single_child(architecture, "layout", loc_data); + process_layout(next, arch, loc_data, num_of_avail_layers); // Precess vib_layout - Next = get_single_child(architecture, "vib_layout", loc_data, ReqOpt::OPTIONAL); - if (Next) { - process_vib_layout(Next, arch, loc_data); + next = get_single_child(architecture, "vib_layout", loc_data, ReqOpt::OPTIONAL); + if (next) { + process_vib_layout(next, arch, loc_data); } - /* Process device */ - Next = get_single_child(architecture, "device", loc_data); - process_device(Next, arch, arch_def_fc, loc_data); + // Process device + next = get_single_child(architecture, "device", loc_data); + process_device(next, arch, arch_def_fc, loc_data); - /* Process switches */ - Next = get_single_child(architecture, "switchlist", loc_data); - arch->switches = process_switches(Next, timing_enabled, loc_data); + // Process switches + next = get_single_child(architecture, "switchlist", loc_data); + arch->switches = process_switches(next, timing_enabled, loc_data); // Process switchblocks. This depends on switches bool switchblocklist_required = (arch->sb_type == e_switch_block_type::CUSTOM); // require this section only if custom switchblocks are used SWITCHBLOCKLIST_REQD = BoolToReqOpt(switchblocklist_required); - /* Process segments. This depends on switches */ - Next = get_single_child(architecture, "segmentlist", loc_data); - arch->Segments = process_segments(Next, arch->switches, num_of_avail_layers, timing_enabled, switchblocklist_required, loc_data); + // Process segments. This depends on switches + next = get_single_child(architecture, "segmentlist", loc_data); + arch->Segments = process_segments(next, arch->switches, num_of_avail_layers, timing_enabled, switchblocklist_required, loc_data); - Next = get_single_child(architecture, "switchblocklist", loc_data, SWITCHBLOCKLIST_REQD); - if (Next) { - process_switch_blocks(Next, arch, loc_data); + next = get_single_child(architecture, "switchblocklist", loc_data, SWITCHBLOCKLIST_REQD); + if (next) { + process_switch_blocks(next, arch, loc_data); } - /* Process logical block types */ - Next = get_single_child(architecture, "complexblocklist", loc_data); - process_complex_blocks(Next, LogicalBlockTypes, *arch, timing_enabled, loc_data); + // Process logical block types + next = get_single_child(architecture, "complexblocklist", loc_data); + process_complex_blocks(next, LogicalBlockTypes, *arch, timing_enabled, loc_data); - /* Process logical block types */ - Next = get_single_child(architecture, "tiles", loc_data); - process_tiles(Next, PhysicalTileTypes, LogicalBlockTypes, arch_def_fc, *arch, loc_data, num_of_avail_layers); + // Process logical block types + next = get_single_child(architecture, "tiles", loc_data); + process_tiles(next, PhysicalTileTypes, LogicalBlockTypes, arch_def_fc, *arch, loc_data, num_of_avail_layers); - /* Link Physical Tiles with Logical Blocks */ + // Link Physical Tiles with Logical Blocks link_physical_logical_types(PhysicalTileTypes, LogicalBlockTypes); - /* Process directs */ - Next = get_single_child(architecture, "directlist", loc_data, ReqOpt::OPTIONAL); - if (Next) { - arch->directs = process_directs(Next, arch->switches, loc_data); + // Process directs + next = get_single_child(architecture, "directlist", loc_data, ReqOpt::OPTIONAL); + if (next) { + arch->directs = process_directs(next, arch->switches, loc_data); } // Process vib_arch - Next = get_single_child(architecture, "vib_arch", loc_data, ReqOpt::OPTIONAL); - if (Next) { - process_vib_arch(Next, arch, loc_data); + next = get_single_child(architecture, "vib_arch", loc_data, ReqOpt::OPTIONAL); + if (next) { + process_vib_arch(next, arch, loc_data); } // Process Clock Networks - Next = get_single_child(architecture, "clocknetworks", loc_data, ReqOpt::OPTIONAL); - if (Next) { + next = get_single_child(architecture, "clocknetworks", loc_data, ReqOpt::OPTIONAL); + if (next) { std::vector expected_children = {"metal_layers", "clock_network", "clock_routing"}; - expect_only_children(Next, expected_children, loc_data); + expect_only_children(next, expected_children, loc_data); - process_clock_metal_layers(Next, arch->clock_arch.clock_metal_layers, loc_data); + process_clock_metal_layers(next, arch->clock_arch.clock_metal_layers, loc_data); - process_clock_networks(Next, + process_clock_networks(next, arch->clock_arch.clock_networks_arch, arch->switches, loc_data); - process_clock_routing(Next, + process_clock_routing(next, arch->clock_arch.clock_connections_arch, arch->switches, loc_data); @@ -525,40 +525,40 @@ void xml_read_arch(const char* ArchFile, POWER_REQD = ReqOpt::OPTIONAL; } - Next = get_single_child(architecture, "power", loc_data, POWER_REQD); - if (Next) { + next = get_single_child(architecture, "power", loc_data, POWER_REQD); + if (next) { if (arch->power) { - process_power(Next, arch->power, loc_data); + process_power(next, arch->power, loc_data); } else { // This information still needs to be read, even if it is just thrown away. t_power_arch* power_arch_fake = new t_power_arch(); - process_power(Next, power_arch_fake, loc_data); + process_power(next, power_arch_fake, loc_data); delete power_arch_fake; } } // Process Clocks - Next = get_single_child(architecture, "clocks", loc_data, POWER_REQD); - if (Next) { + next = get_single_child(architecture, "clocks", loc_data, POWER_REQD); + if (next) { if (arch->clocks) { - process_clocks(Next, *arch->clocks, loc_data); + process_clocks(next, *arch->clocks, loc_data); } else { // This information still needs to be read, even if it is just thrown away. std::vector clocks_fake; - process_clocks(Next, clocks_fake, loc_data); + process_clocks(next, clocks_fake, loc_data); } } // process NoC (optional) - Next = get_single_child(architecture, "noc", loc_data, pugiutil::OPTIONAL); - if (Next) { - process_noc_tag(Next, arch, loc_data); + next = get_single_child(architecture, "noc", loc_data, pugiutil::OPTIONAL); + if (next) { + process_noc_tag(next, arch, loc_data); } // Process scatter-gather patterns (optional) - Next = get_single_child(architecture, "scatter_gather_list", loc_data, pugiutil::OPTIONAL); - if (Next) { - process_sg_tag(Next, arch, loc_data, arch->switches); + next = get_single_child(architecture, "scatter_gather_list", loc_data, pugiutil::OPTIONAL); + if (next) { + process_sg_tag(next, arch, loc_data, arch->switches); } SyncModelsPbTypes(arch, LogicalBlockTypes); From 4f10eb2cdeeede61f870be0b0e5e379d65f0793b Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 14:28:15 -0400 Subject: [PATCH 04/14] join declaration and assignment + renmae some vars --- libs/libarchfpga/src/read_xml_arch_file.cpp | 1130 +++++++++---------- libs/libarchfpga/src/read_xml_arch_file.h | 6 +- 2 files changed, 543 insertions(+), 593 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 319df1e394..2352642229 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -132,14 +132,14 @@ static std::pair process_pin_string(pugi::xml_node Locations, * If no instance range is explicitly defined, we assume the range of type capacity, i.e., (0, capacity - 1) */ static std::pair process_instance_string(pugi::xml_node Locations, - t_sub_tile& sub_tile, + const t_sub_tile& sub_tile, const char* pin_loc_string, const pugiutil::loc_data& loc_data); /* Process XML hierarchy */ static void process_tiles(pugi::xml_node node, - std::vector& PhysicalTileTypes, - std::vector& LogicalBlockTypes, + std::vector& physical_tile_types, + std::vector& logical_block_types, const t_default_fc_spec& arch_def_fc, t_arch& arch, const pugiutil::loc_data& loc_data, @@ -148,10 +148,10 @@ static void process_tiles(pugi::xml_node node, // TODO: Remove block_type_contains_blif_model / pb_type_contains_blif_model // as part of // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193 -static void mark_IO_types(std::vector& PhysicalTileTypes); +static void mark_IO_types(std::vector& physical_tile_types); static void process_tile_props(pugi::xml_node node, - t_physical_tile_type* PhysicalTileType, + t_physical_tile_type* physical_tile_type, const pugiutil::loc_data& loc_data); static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, @@ -164,31 +164,31 @@ static void process_tile_port(pugi::xml_node node, static void process_tile_equivalent_sites(pugi::xml_node Parent, t_sub_tile* sub_tile, - t_physical_tile_type* PhysicalTileType, - std::vector& LogicalBlockTypes, + t_physical_tile_type* physical_tile_type, + std::vector& logical_block_types, const pugiutil::loc_data& loc_data); static void process_equivalent_site_direct_connection(pugi::xml_node Parent, t_sub_tile* sub_tile, - t_physical_tile_type* PhysicalTileType, - t_logical_block_type* LogicalBlockType, + t_physical_tile_type* physical_tile_type, + const t_logical_block_type* logical_block_type, const pugiutil::loc_data& loc_data); static void process_equivalent_site_custom_connection(pugi::xml_node Parent, t_sub_tile* sub_tile, - t_physical_tile_type* PhysicalTileType, - t_logical_block_type* LogicalBlockType, + t_physical_tile_type* physical_tile_type, + const t_logical_block_type* logical_block_type, const std::string& site_name, const pugiutil::loc_data& loc_data); static void process_pin_locations(pugi::xml_node Locations, - t_physical_tile_type* PhysicalTileType, + t_physical_tile_type* physical_tile_type, t_sub_tile* sub_tile, t_pin_locs* pin_locs, const pugiutil::loc_data& loc_data, const int num_of_avail_layer); static void process_sub_tiles(pugi::xml_node node, - t_physical_tile_type* PhysicalTileType, - std::vector& LogicalBlockTypes, - std::vector& segments, + t_physical_tile_type* physical_tile_type, + std::vector& logical_block_types, + const std::vector& segments, const t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data, int num_of_avail_layer); @@ -264,10 +264,10 @@ static void process_mode(pugi::xml_node Parent, static void process_fc_values(pugi::xml_node node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data); static void process_fc(pugi::xml_node node, - t_physical_tile_type* PhysicalTileType, + t_physical_tile_type* physical_tile_type, t_sub_tile* sub_tile, t_pin_counts pin_counts, - std::vector& segments, + const std::vector& segments, const t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data); static t_fc_override process_fc_override(pugi::xml_node node, const pugiutil::loc_data& loc_data); @@ -309,14 +309,14 @@ static void process_tileable_device_parameters(t_arch* arch, const pugiutil::loc * @brief Parses tag in the architecture file. * * @param node The xml node referring to tag - * @param LogicalBlockTypes This function fills this vector with all available + * @param logical_block_types This function fills this vector with all available * logical block types. * @param arch Used to access models and string internment storage. * @param timing_enabled Determines whether timing-aware optimizations are enabled. * @param loc_data Points to the location in the xml file where the parser is reading. */ static void process_complex_blocks(pugi::xml_node node, - std::vector& LogicalBlockTypes, + std::vector& logical_block_types, const t_arch& arch, bool timing_enabled, const pugiutil::loc_data& loc_data); @@ -345,7 +345,7 @@ static void process_clock_switch_points(pugi::xml_node parent, static void process_clock_routing(pugi::xml_node parent, std::vector& clock_connections, const std::vector& switches, - pugiutil::loc_data& loc_data); + const pugiutil::loc_data& loc_data); static std::vector process_segments(pugi::xml_node parent, const std::vector& switches, @@ -396,43 +396,42 @@ static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int */ /* Loads the given architecture file. */ -void xml_read_arch(const char* ArchFile, +void xml_read_arch(const char* arch_file, const bool timing_enabled, t_arch* arch, - std::vector& PhysicalTileTypes, - std::vector& LogicalBlockTypes) { - pugi::xml_node next; - ReqOpt POWER_REQD, SWITCHBLOCKLIST_REQD; - - if (!vtr::check_file_name_extension(ArchFile, ".xml")) { + std::vector& physical_tile_types, + std::vector& logical_block_types) { + if (!vtr::check_file_name_extension(arch_file, ".xml")) { VTR_LOG_WARN( "Architecture file '%s' may be in incorrect format. " "Expecting .xml format for architecture files.\n", - ArchFile); + arch_file); } //Create a unique identifier for this architecture file based on it's contents - arch->architecture_id = vtr::strdup(vtr::secure_digest_file(ArchFile).c_str()); + arch->architecture_id = vtr::strdup(vtr::secure_digest_file(arch_file).c_str()); - /* Parse the file */ - pugi::xml_document doc; - pugiutil::loc_data loc_data; - t_default_fc_spec arch_def_fc; + // Parse the file try { - loc_data = pugiutil::load_xml(doc, ArchFile); + ReqOpt SWITCHBLOCKLIST_REQD; + ReqOpt POWER_REQD; + t_default_fc_spec arch_def_fc; + pugi::xml_document doc; + pugi::xml_node next; + pugiutil::loc_data loc_data = pugiutil::load_xml(doc, arch_file); - set_arch_file_name(ArchFile); + set_arch_file_name(arch_file); /* Root node should be architecture */ auto architecture = get_single_child(doc, "architecture", loc_data); /* TODO: do version processing properly with string delimiting on the . */ #if 0 - char* Prop = get_attribute(architecture, "version", loc_data, ReqOpt::OPTIONAL).as_string(NULL); - if (Prop != NULL) { - if (atof(Prop) > atof(VPR_VERSION)) { + char* prop = get_attribute(architecture, "version", loc_data, ReqOpt::OPTIONAL).as_string(NULL); + if (prop != NULL) { + if (atof(prop) > atof(VPR_VERSION)) { VTR_LOG_WARN( "This architecture version is for VPR %f while your current VPR version is " VPR_VERSION ", compatability issues may arise\n", - atof(Prop)); + atof(prop)); } } #endif @@ -475,14 +474,14 @@ void xml_read_arch(const char* ArchFile, // Process logical block types next = get_single_child(architecture, "complexblocklist", loc_data); - process_complex_blocks(next, LogicalBlockTypes, *arch, timing_enabled, loc_data); + process_complex_blocks(next, logical_block_types, *arch, timing_enabled, loc_data); // Process logical block types next = get_single_child(architecture, "tiles", loc_data); - process_tiles(next, PhysicalTileTypes, LogicalBlockTypes, arch_def_fc, *arch, loc_data, num_of_avail_layers); + process_tiles(next, physical_tile_types, logical_block_types, arch_def_fc, *arch, loc_data, num_of_avail_layers); // Link Physical Tiles with Logical Blocks - link_physical_logical_types(PhysicalTileTypes, LogicalBlockTypes); + link_physical_logical_types(physical_tile_types, logical_block_types); // Process directs next = get_single_child(architecture, "directlist", loc_data, ReqOpt::OPTIONAL); @@ -561,12 +560,12 @@ void xml_read_arch(const char* ArchFile, process_sg_tag(next, arch, loc_data, arch->switches); } - SyncModelsPbTypes(arch, LogicalBlockTypes); + SyncModelsPbTypes(arch, logical_block_types); check_models(arch); - mark_IO_types(PhysicalTileTypes); + mark_IO_types(physical_tile_types); } catch (pugiutil::XmlError& e) { - archfpga_throw(ArchFile, e.line(), e.what()); + archfpga_throw(arch_file, e.line(), e.what()); } } @@ -772,7 +771,7 @@ static void load_pin_loc(pugi::xml_node Locations, } static std::pair process_instance_string(pugi::xml_node Locations, - t_sub_tile& sub_tile, + const t_sub_tile& sub_tile, const char* pin_loc_string, const pugiutil::loc_data& loc_data) { Tokens tokens(pin_loc_string); @@ -989,7 +988,7 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, t_pb_type* parent_pb_type, const pugiutil::loc_data& loc_data) { int i = 0; - const char* Prop; + const char* prop; if (get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr)) { i++; @@ -1016,54 +1015,54 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, if (0 == strcmp(Parent.name(), "delay_constant")) { annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; - Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if (Prop) { - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MAX, Prop}; + prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if (prop) { + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MAX, prop}; i++; } - Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if (Prop) { - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MIN, Prop}; + prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if (prop) { + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MIN, prop}; i++; } - Prop = get_attribute(Parent, "in_port", loc_data).value(); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "in_port", loc_data).value(); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "out_port", loc_data).value(); - annotation->output_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "out_port", loc_data).value(); + annotation->output_pins = vtr::strdup(prop); } else if (0 == strcmp(Parent.name(), "delay_matrix")) { annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX; - Prop = get_attribute(Parent, "type", loc_data).value(); + prop = get_attribute(Parent, "type", loc_data).value(); annotation->annotation_entries[i].second = Parent.child_value(); - if (0 == strcmp(Prop, "max")) { + if (0 == strcmp(prop, "max")) { annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX; } else { - VTR_ASSERT(0 == strcmp(Prop, "min")); + VTR_ASSERT(0 == strcmp(prop, "min")); annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN; } i++; - Prop = get_attribute(Parent, "in_port", loc_data).value(); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "in_port", loc_data).value(); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "out_port", loc_data).value(); - annotation->output_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "out_port", loc_data).value(); + annotation->output_pins = vtr::strdup(prop); } else if (0 == strcmp(Parent.name(), "C_constant")) { annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; - Prop = get_attribute(Parent, "C", loc_data).value(); - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Prop}; + prop = get_attribute(Parent, "C", loc_data).value(); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, prop}; i++; - Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->output_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + annotation->output_pins = vtr::strdup(prop); VTR_ASSERT(annotation->output_pins != nullptr || annotation->input_pins != nullptr); } else if (0 == strcmp(Parent.name(), "C_matrix")) { @@ -1072,41 +1071,41 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Parent.child_value()}; i++; - Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->output_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + annotation->output_pins = vtr::strdup(prop); VTR_ASSERT(annotation->output_pins != nullptr || annotation->input_pins != nullptr); } else if (0 == strcmp(Parent.name(), "T_setup")) { annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; - Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_TSETUP, Prop}; + prop = get_attribute(Parent, "value", loc_data).value(); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_TSETUP, prop}; i++; - Prop = get_attribute(Parent, "port", loc_data).value(); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "port", loc_data).value(); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "clock", loc_data).value(); - annotation->clock = vtr::strdup(Prop); + prop = get_attribute(Parent, "clock", loc_data).value(); + annotation->clock = vtr::strdup(prop); primitives_annotation_clock_match(annotation, parent_pb_type); } else if (0 == strcmp(Parent.name(), "T_clock_to_Q")) { annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; - Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); bool found_min_max_attrib = false; - if (Prop) { - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX, Prop}; + if (prop) { + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX, prop}; i++; found_min_max_attrib = true; } - Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if (Prop) { - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN, Prop}; + prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if (prop) { + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN, prop}; i++; found_min_max_attrib = true; } @@ -1118,41 +1117,41 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, .c_str()); } - Prop = get_attribute(Parent, "port", loc_data).value(); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "port", loc_data).value(); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "clock", loc_data).value(); - annotation->clock = vtr::strdup(Prop); + prop = get_attribute(Parent, "clock", loc_data).value(); + annotation->clock = vtr::strdup(prop); primitives_annotation_clock_match(annotation, parent_pb_type); } else if (0 == strcmp(Parent.name(), "T_hold")) { annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; - Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_THOLD, Prop}; + prop = get_attribute(Parent, "value", loc_data).value(); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_THOLD, prop}; i++; - Prop = get_attribute(Parent, "port", loc_data).value(); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "port", loc_data).value(); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "clock", loc_data).value(); - annotation->clock = vtr::strdup(Prop); + prop = get_attribute(Parent, "clock", loc_data).value(); + annotation->clock = vtr::strdup(prop); primitives_annotation_clock_match(annotation, parent_pb_type); } else if (0 == strcmp(Parent.name(), "pack_pattern")) { annotation->type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; - Prop = get_attribute(Parent, "name", loc_data).value(); - annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, Prop}; + prop = get_attribute(Parent, "name", loc_data).value(); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, prop}; i++; - Prop = get_attribute(Parent, "in_port", loc_data).value(); - annotation->input_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "in_port", loc_data).value(); + annotation->input_pins = vtr::strdup(prop); - Prop = get_attribute(Parent, "out_port", loc_data).value(); - annotation->output_pins = vtr::strdup(Prop); + prop = get_attribute(Parent, "out_port", loc_data).value(); + annotation->output_pins = vtr::strdup(prop); } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), @@ -1166,16 +1165,13 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, } static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) { - pugi::xml_node cur; - const char* prop; - t_port* port; int high, low; - cur = get_first_child(parent, "port", loc_data, ReqOpt::OPTIONAL); + pugi::xml_node cur = get_first_child(parent, "port", loc_data, ReqOpt::OPTIONAL); while (cur) { - prop = get_attribute(cur, "name", loc_data).value(); + const char* prop = get_attribute(cur, "name", loc_data).value(); - port = findPortByName(prop, pb_type, &high, &low); + t_port* port = findPortByName(prop, pb_type, &high, &low); if (!port) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Could not find port '%s' needed for energy per toggle.", @@ -1230,12 +1226,12 @@ static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_ty } static void ProcessPb_TypePower(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) { - pugi::xml_node cur, child; + pugi::xml_node child; bool require_dynamic_absolute = false; bool require_static_absolute = false; bool require_dynamic_C_internal = false; - cur = get_first_child(Parent, "power", loc_data, ReqOpt::OPTIONAL); + pugi::xml_node cur = get_first_child(Parent, "power", loc_data, ReqOpt::OPTIONAL); if (!cur) { return; } @@ -1276,14 +1272,10 @@ static void ProcessPb_TypePower(pugi::xml_node Parent, t_pb_type* pb_type, const } static void process_pb_type_power_est_method(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) { - pugi::xml_node cur; - const char* prop; - e_power_estimation_method parent_power_method; + const char* prop = nullptr; - prop = nullptr; - - cur = get_first_child(Parent, "power", loc_data, ReqOpt::OPTIONAL); + pugi::xml_node cur = get_first_child(Parent, "power", loc_data, ReqOpt::OPTIONAL); if (cur) { prop = get_attribute(cur, "method", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); } @@ -1327,8 +1319,8 @@ static void process_pb_type(pugi::xml_node Parent, const t_arch& arch, const pugiutil::loc_data& loc_data, int& pb_idx) { - const char* Prop; - pugi::xml_node Cur; + const char* prop; + pugi::xml_node cur; bool is_root_pb_type = (mode == nullptr || mode->parent_pb_type == nullptr); bool is_leaf_pb_type = bool(get_attribute(Parent, "blif_model", loc_data, ReqOpt::OPTIONAL)); @@ -1366,19 +1358,19 @@ static void process_pb_type(pugi::xml_node Parent, pb_type->index_in_logical_block = pb_idx; if (mode != nullptr && mode->parent_pb_type != nullptr) { pb_type->depth = mode->parent_pb_type->depth + 1; - Prop = get_attribute(Parent, "name", loc_data).value(); - pb_type->name = vtr::strdup(Prop); + prop = get_attribute(Parent, "name", loc_data).value(); + pb_type->name = vtr::strdup(prop); } else { pb_type->depth = 0; /* same name as type */ } - Prop = get_attribute(Parent, "blif_model", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - pb_type->blif_model = vtr::strdup(Prop); + prop = get_attribute(Parent, "blif_model", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + pb_type->blif_model = vtr::strdup(prop); pb_type->class_type = UNKNOWN_CLASS; - Prop = get_attribute(Parent, "class", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - char* class_name = vtr::strdup(Prop); + prop = get_attribute(Parent, "class", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + char* class_name = vtr::strdup(prop); if (class_name) { if (0 == strcmp(class_name, PB_TYPE_CLASS_STRING[LUT_CLASS])) { @@ -1435,14 +1427,14 @@ static void process_pb_type(pugi::xml_node Parent, std::set pb_port_names; for (const char* child_name : {"input", "output", "clock"}) { - Cur = get_first_child(Parent, child_name, loc_data, ReqOpt::OPTIONAL); + cur = get_first_child(Parent, child_name, loc_data, ReqOpt::OPTIONAL); int port_index_by_type = 0; - while (Cur) { + while (cur) { pb_type->ports[port_idx].parent_pb_type = pb_type; pb_type->ports[port_idx].index = port_idx; pb_type->ports[port_idx].port_index_by_type = port_index_by_type; - process_pb_type_port(Cur, &pb_type->ports[port_idx], + process_pb_type_port(cur, &pb_type->ports[port_idx], pb_type->pb_type_power->estimation_method, is_root_pb_type, loc_data); pb_type->ports[port_idx].absolute_first_pin_index = absolute_port_first_pin_index; @@ -1451,7 +1443,7 @@ static void process_pb_type(pugi::xml_node Parent, //Check port name duplicates auto [_, success] = pb_port_names.insert(pb_type->ports[port_idx].name); if (!success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate port names in pb_type '%s': port '%s'\n", pb_type->name, pb_type->ports[port_idx].name) .c_str()); @@ -1460,7 +1452,7 @@ static void process_pb_type(pugi::xml_node Parent, /* get next iteration */ port_idx++; port_index_by_type++; - Cur = Cur.next_sibling(Cur.name()); + cur = cur.next_sibling(cur.name()); } } @@ -1505,14 +1497,14 @@ static void process_pb_type(pugi::xml_node Parent, int annotation_idx = 0; for (auto child_name : {"delay_constant", "delay_matrix", "C_constant", "C_matrix", "T_setup", "T_clock_to_Q", "T_hold"}) { - Cur = get_first_child(Parent, child_name, loc_data, ReqOpt::OPTIONAL); + cur = get_first_child(Parent, child_name, loc_data, ReqOpt::OPTIONAL); - while (Cur) { - process_pin_to_pin_annotations(Cur, &pb_type->annotations[annotation_idx], pb_type, loc_data); + while (cur) { + process_pin_to_pin_annotations(cur, &pb_type->annotations[annotation_idx], pb_type, loc_data); /* get next iteration */ annotation_idx++; - Cur = Cur.next_sibling(Cur.name()); + cur = cur.next_sibling(cur.name()); } } VTR_ASSERT(annotation_idx == num_annotations); @@ -1552,16 +1544,16 @@ static void process_pb_type(pugi::xml_node Parent, // STL set for checking duplicate mode names std::set mode_names; - Cur = get_first_child(Parent, "mode", loc_data); - while (Cur != nullptr) { - if (0 == strcmp(Cur.name(), "mode")) { + cur = get_first_child(Parent, "mode", loc_data); + while (cur != nullptr) { + if (0 == strcmp(cur.name(), "mode")) { pb_type->modes[mode_idx].parent_pb_type = pb_type; pb_type->modes[mode_idx].index = mode_idx; - process_mode(Cur, &pb_type->modes[mode_idx], timing_enabled, arch, loc_data, pb_idx); + process_mode(cur, &pb_type->modes[mode_idx], timing_enabled, arch, loc_data, pb_idx); auto [_, success] = mode_names.insert(pb_type->modes[mode_idx].name); if (!success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate mode name: '%s' in pb_type '%s'.\n", pb_type->modes[mode_idx].name, pb_type->name) .c_str()); @@ -1569,7 +1561,7 @@ static void process_pb_type(pugi::xml_node Parent, /* get next iteration */ mode_idx++; - Cur = Cur.next_sibling(Cur.name()); + cur = cur.next_sibling(cur.name()); } } } @@ -1581,10 +1573,6 @@ static void process_pb_type(pugi::xml_node Parent, } static void process_pb_type_port_power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data) { - pugi::xml_node cur; - const char* prop; - bool wire_defined = false; - port->port_power = new t_port_power(); //Defaults @@ -1596,13 +1584,13 @@ static void process_pb_type_port_power(pugi::xml_node Parent, t_port* port, e_po port->port_power->buffer_type = POWER_BUFFER_TYPE_NONE; } - cur = get_single_child(Parent, "power", loc_data, ReqOpt::OPTIONAL); - + pugi::xml_node cur = get_single_child(Parent, "power", loc_data, ReqOpt::OPTIONAL); if (cur) { - /* Wire capacitance */ + bool wire_defined = false; + // Wire capacitance - /* Absolute C provided */ - prop = get_attribute(cur, "wire_capacitance", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + // Absolute C provided + const char* prop = get_attribute(cur, "wire_capacitance", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (prop) { if (!(power_method == POWER_METHOD_AUTO_SIZES || power_method == POWER_METHOD_SPECIFY_SIZES)) { @@ -1693,29 +1681,28 @@ static void process_pb_type_port(pugi::xml_node Parent, t_port* port, e_power_es expect_only_attributes(Parent, expected_attributes, loc_data); - const char* Prop; - Prop = get_attribute(Parent, "name", loc_data).value(); - port->name = vtr::strdup(Prop); + const char* prop = get_attribute(Parent, "name", loc_data).value(); + port->name = vtr::strdup(prop); - Prop = get_attribute(Parent, "port_class", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - port->port_class = vtr::strdup(Prop); + prop = get_attribute(Parent, "port_class", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + port->port_class = vtr::strdup(prop); - Prop = get_attribute(Parent, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if (Prop) { - if (Prop == "none"s) { + prop = get_attribute(Parent, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if (prop) { + if (prop == "none"s) { port->equivalent = PortEquivalence::NONE; - } else if (Prop == "full"s) { + } else if (prop == "full"s) { port->equivalent = PortEquivalence::FULL; - } else if (Prop == "instance"s) { + } else if (prop == "instance"s) { if (Parent.name() == "output"s) { port->equivalent = PortEquivalence::INSTANCE; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - vtr::string_fmt("Invalid pin equivalence '%s' for %s port.", Prop, Parent.name()).c_str()); + vtr::string_fmt("Invalid pin equivalence '%s' for %s port.", prop, Parent.name()).c_str()); } } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - vtr::string_fmt("Invalid pin equivalence '%s'.", Prop).c_str()); + vtr::string_fmt("Invalid pin equivalence '%s'.", prop).c_str()); } } port->num_pins = get_attribute(Parent, "num_pins", loc_data).as_int(0); @@ -1831,8 +1818,6 @@ static void process_interconnect(vtr::string_internment& strings, pugi::xml_node Parent, t_mode* mode, const pugiutil::loc_data& loc_data) { - const char* Prop; - // used to find duplicate names std::set interconnect_names; @@ -1847,36 +1832,36 @@ static void process_interconnect(vtr::string_internment& strings, int interconnect_idx = 0; for (auto child_name : {"complete", "direct", "mux"}) { - pugi::xml_node Cur = get_first_child(Parent, child_name, loc_data, ReqOpt::OPTIONAL); + pugi::xml_node cur = get_first_child(Parent, child_name, loc_data, ReqOpt::OPTIONAL); - while (Cur != nullptr) { - if (0 == strcmp(Cur.name(), "complete")) { + while (cur != nullptr) { + if (0 == strcmp(cur.name(), "complete")) { mode->interconnect[interconnect_idx].type = COMPLETE_INTERC; - } else if (0 == strcmp(Cur.name(), "direct")) { + } else if (0 == strcmp(cur.name(), "direct")) { mode->interconnect[interconnect_idx].type = DIRECT_INTERC; } else { - VTR_ASSERT(0 == strcmp(Cur.name(), "mux")); + VTR_ASSERT(0 == strcmp(cur.name(), "mux")); mode->interconnect[interconnect_idx].type = MUX_INTERC; } - mode->interconnect[interconnect_idx].line_num = loc_data.line(Cur); + mode->interconnect[interconnect_idx].line_num = loc_data.line(cur); mode->interconnect[interconnect_idx].parent_mode_index = mode->index; mode->interconnect[interconnect_idx].parent_mode = mode; - Prop = get_attribute(Cur, "input", loc_data).value(); - mode->interconnect[interconnect_idx].input_string = vtr::strdup(Prop); + const char* prop = get_attribute(cur, "input", loc_data).value(); + mode->interconnect[interconnect_idx].input_string = vtr::strdup(prop); - Prop = get_attribute(Cur, "output", loc_data).value(); - mode->interconnect[interconnect_idx].output_string = vtr::strdup(Prop); + prop = get_attribute(cur, "output", loc_data).value(); + mode->interconnect[interconnect_idx].output_string = vtr::strdup(prop); - Prop = get_attribute(Cur, "name", loc_data).value(); - mode->interconnect[interconnect_idx].name = vtr::strdup(Prop); - mode->interconnect[interconnect_idx].meta = process_meta_data(strings, Cur, loc_data); + prop = get_attribute(cur, "name", loc_data).value(); + mode->interconnect[interconnect_idx].name = vtr::strdup(prop); + mode->interconnect[interconnect_idx].meta = process_meta_data(strings, cur, loc_data); auto [_, success] = interconnect_names.insert(mode->interconnect[interconnect_idx].name); if (!success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate interconnect name: '%s' in mode: '%s'.\n", mode->interconnect[interconnect_idx].name, mode->name) .c_str()); @@ -1885,22 +1870,22 @@ static void process_interconnect(vtr::string_internment& strings, /* Process delay and capacitance annotations */ int num_annotations = 0; for (auto annot_child_name : {"delay_constant", "delay_matrix", "C_constant", "C_matrix", "pack_pattern"}) { - num_annotations += count_children(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); + num_annotations += count_children(cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); } mode->interconnect[interconnect_idx].annotations.resize(num_annotations); int annotation_idx = 0; for (auto annot_child_name : {"delay_constant", "delay_matrix", "C_constant", "C_matrix", "pack_pattern"}) { - pugi::xml_node Cur2 = get_first_child(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); + pugi::xml_node cur2 = get_first_child(cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); - while (Cur2 != nullptr) { - process_pin_to_pin_annotations(Cur2, + while (cur2 != nullptr) { + process_pin_to_pin_annotations(cur2, &(mode->interconnect[interconnect_idx].annotations[annotation_idx]), nullptr, loc_data); /* get next iteration */ annotation_idx++; - Cur2 = Cur2.next_sibling(Cur2.name()); + cur2 = cur2.next_sibling(cur2.name()); } } VTR_ASSERT(annotation_idx == num_annotations); @@ -1910,7 +1895,7 @@ static void process_interconnect(vtr::string_internment& strings, mode->interconnect[interconnect_idx].interconnect_power->port_info_initialized = false; /* get next iteration */ - Cur = Cur.next_sibling(Cur.name()); + cur = cur.next_sibling(cur.name()); interconnect_idx++; } } @@ -1924,15 +1909,14 @@ static void process_mode(pugi::xml_node Parent, const t_arch& arch, const pugiutil::loc_data& loc_data, int& parent_pb_idx) { - const char* Prop; - pugi::xml_node Cur; + pugi::xml_node cur; bool implied_mode = (0 == strcmp(Parent.name(), "pb_type")); if (implied_mode) { mode->name = vtr::strdup("default"); } else { - Prop = get_attribute(Parent, "name", loc_data).value(); - mode->name = vtr::strdup(Prop); + const char* prop = get_attribute(Parent, "name", loc_data).value(); + mode->name = vtr::strdup(prop); } /* Parse XML about if this mode is disabled for packing or not @@ -1963,15 +1947,15 @@ static void process_mode(pugi::xml_node Parent, std::set pb_type_names; int pb_type_child_idx = 0; - Cur = get_first_child(Parent, "pb_type", loc_data); - while (Cur != nullptr) { - if (0 == strcmp(Cur.name(), "pb_type")) { + cur = get_first_child(Parent, "pb_type", loc_data); + while (cur != nullptr) { + if (0 == strcmp(cur.name(), "pb_type")) { parent_pb_idx++; - process_pb_type(Cur, &mode->pb_type_children[pb_type_child_idx], mode, timing_enabled, arch, loc_data, parent_pb_idx); + process_pb_type(cur, &mode->pb_type_children[pb_type_child_idx], mode, timing_enabled, arch, loc_data, parent_pb_idx); auto [_, success] = pb_type_names.insert(mode->pb_type_children[pb_type_child_idx].name); if (!success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate pb_type name: '%s' in mode: '%s'.\n", mode->pb_type_children[pb_type_child_idx].name, mode->name) .c_str()); @@ -1979,7 +1963,7 @@ static void process_mode(pugi::xml_node Parent, /* get next iteration */ pb_type_child_idx++; - Cur = Cur.next_sibling(Cur.name()); + cur = cur.next_sibling(cur.name()); } } } else { @@ -1995,8 +1979,8 @@ static void process_mode(pugi::xml_node Parent, mode->meta = process_meta_data(arch.strings, Parent, loc_data); } - Cur = get_single_child(Parent, "interconnect", loc_data); - process_interconnect(arch.strings, Cur, mode, loc_data); + cur = get_single_child(Parent, "interconnect", loc_data); + process_interconnect(arch.strings, cur, mode, loc_data); } static void process_fc_values(pugi::xml_node node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data) { @@ -2020,10 +2004,10 @@ static void process_fc_values(pugi::xml_node node, t_default_fc_spec& spec, cons /* Takes in the node ptr for the 'fc' elements and initializes * the appropriate fields of type. */ static void process_fc(pugi::xml_node node, - t_physical_tile_type* PhysicalTileType, + t_physical_tile_type* physical_tile_type, t_sub_tile* sub_tile, t_pin_counts pin_counts, - std::vector& segments, + const std::vector& segments, const t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data) { std::vector fc_overrides; @@ -2121,7 +2105,7 @@ static void process_fc(pugi::xml_node node, ++iblk_pin; } - PhysicalTileType->fc_specs.push_back(fc_spec); + physical_tile_type->fc_specs.push_back(fc_spec); } } } @@ -2370,8 +2354,7 @@ static void process_switch_block_locations(pugi::xml_node switchblock_locations, /* Takes in node pointing to and loads all the * child type objects. */ static void process_models(pugi::xml_node node, t_arch* arch, const pugiutil::loc_data& loc_data) { - pugi::xml_node p; - /* std::maps for checking duplicates */ + // std::maps for checking duplicates std::map model_name_map; for (pugi::xml_node model : node.children()) { @@ -2902,8 +2885,6 @@ static void process_block_type_locs(t_grid_def& grid_def, /* Takes in node pointing to and loads all the * child type objects. */ static void process_device(pugi::xml_node node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data) { - const char* Prop; - pugi::xml_node Cur; bool custom_switch_block = false; //Warn that is no longer supported @@ -2920,63 +2901,63 @@ static void process_device(pugi::xml_node node, t_arch* arch, t_default_fc_spec& expect_only_children(node, {"sizing", "area", "chan_width_distr", "switch_block", "connection_block", "default_fc"}, loc_data); // tag - Cur = get_single_child(node, "sizing", loc_data); - expect_only_attributes(Cur, {"R_minW_nmos", "R_minW_pmos"}, loc_data); - arch->R_minW_nmos = get_attribute(Cur, "R_minW_nmos", loc_data).as_float(); - arch->R_minW_pmos = get_attribute(Cur, "R_minW_pmos", loc_data).as_float(); + pugi::xml_node cur = get_single_child(node, "sizing", loc_data); + expect_only_attributes(cur, {"R_minW_nmos", "R_minW_pmos"}, loc_data); + arch->R_minW_nmos = get_attribute(cur, "R_minW_nmos", loc_data).as_float(); + arch->R_minW_pmos = get_attribute(cur, "R_minW_pmos", loc_data).as_float(); // tag - Cur = get_single_child(node, "area", loc_data); - expect_only_attributes(Cur, {"grid_logic_tile_area"}, loc_data); - arch->grid_logic_tile_area = get_attribute(Cur, "grid_logic_tile_area", + cur = get_single_child(node, "area", loc_data); + expect_only_attributes(cur, {"grid_logic_tile_area"}, loc_data); + arch->grid_logic_tile_area = get_attribute(cur, "grid_logic_tile_area", loc_data, ReqOpt::OPTIONAL) .as_float(0); // tag - Cur = get_single_child(node, "chan_width_distr", loc_data, ReqOpt::OPTIONAL); - expect_only_attributes(Cur, {}, loc_data); - if (Cur != nullptr) { - process_chan_width_distr(Cur, arch, loc_data); + cur = get_single_child(node, "chan_width_distr", loc_data, ReqOpt::OPTIONAL); + expect_only_attributes(cur, {}, loc_data); + if (cur != nullptr) { + process_chan_width_distr(cur, arch, loc_data); } // tag - Cur = get_single_child(node, "connection_block", loc_data); - expect_only_attributes(Cur, {"input_switch_name", "input_inter_die_switch_name"}, loc_data); - arch->ipin_cblock_switch_name.emplace_back(get_attribute(Cur, "input_switch_name", loc_data).as_string()); - std::string inter_die_conn = get_attribute(Cur, "input_inter_die_switch_name", loc_data, ReqOpt::OPTIONAL).as_string(""); + cur = get_single_child(node, "connection_block", loc_data); + expect_only_attributes(cur, {"input_switch_name", "input_inter_die_switch_name"}, loc_data); + arch->ipin_cblock_switch_name.emplace_back(get_attribute(cur, "input_switch_name", loc_data).as_string()); + std::string inter_die_conn = get_attribute(cur, "input_inter_die_switch_name", loc_data, ReqOpt::OPTIONAL).as_string(""); if (inter_die_conn != "") { arch->ipin_cblock_switch_name.push_back(inter_die_conn); } // tag - Cur = get_single_child(node, "switch_block", loc_data); - expect_only_attributes(Cur, {"type", "fs", "sub_type", "sub_fs"}, loc_data); - Prop = get_attribute(Cur, "type", loc_data).value(); + cur = get_single_child(node, "switch_block", loc_data); + expect_only_attributes(cur, {"type", "fs", "sub_type", "sub_fs"}, loc_data); + const char* prop = get_attribute(cur, "type", loc_data).value(); // Parse attribute 'type', representing the major connectivity pattern for switch blocks - if (strcmp(Prop, "wilton") == 0) { + if (strcmp(prop, "wilton") == 0) { arch->sb_type = e_switch_block_type::WILTON; - } else if (strcmp(Prop, "universal") == 0) { + } else if (strcmp(prop, "universal") == 0) { arch->sb_type = e_switch_block_type::UNIVERSAL; - } else if (strcmp(Prop, "subset") == 0) { + } else if (strcmp(prop, "subset") == 0) { arch->sb_type = e_switch_block_type::SUBSET; - } else if (strcmp(Prop, "custom") == 0) { + } else if (strcmp(prop, "custom") == 0) { arch->sb_type = e_switch_block_type::CUSTOM; custom_switch_block = true; } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), - vtr::string_fmt("Unknown property %s for switch block type x\n", Prop).c_str()); + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), + vtr::string_fmt("Unknown property %s for switch block type x\n", prop).c_str()); } ReqOpt custom_switchblock_reqd = BoolToReqOpt(!custom_switch_block); - arch->Fs = get_attribute(Cur, "fs", loc_data, custom_switchblock_reqd).as_int(3); + arch->Fs = get_attribute(cur, "fs", loc_data, custom_switchblock_reqd).as_int(3); process_tileable_device_parameters(arch, loc_data); - Cur = get_single_child(node, "default_fc", loc_data, ReqOpt::OPTIONAL); - if (Cur) { + cur = get_single_child(node, "default_fc", loc_data, ReqOpt::OPTIONAL); + if (cur) { arch_def_fc.specified = true; - expect_only_attributes(Cur, {"in_type", "in_val", "out_type", "out_val"}, loc_data); - process_fc_values(Cur, arch_def_fc, loc_data); + expect_only_attributes(cur, {"in_type", "in_val", "out_type", "out_val"}, loc_data); + process_fc_values(cur, arch_def_fc, loc_data); } else { arch_def_fc.specified = false; } @@ -3014,40 +2995,37 @@ static void process_tileable_device_parameters(t_arch* arch, const pugiutil::loc static void process_chan_width_distr(pugi::xml_node node, t_arch* arch, const pugiutil::loc_data& loc_data) { - pugi::xml_node Cur; - expect_only_children(node, {"x", "y"}, loc_data); - Cur = get_single_child(node, "x", loc_data); - process_chan_width_distr_dir(Cur, &arch->Chans.chan_x_dist, loc_data); + pugi::xml_node cur = get_single_child(node, "x", loc_data); + process_chan_width_distr_dir(cur, &arch->Chans.chan_x_dist, loc_data); - Cur = get_single_child(node, "y", loc_data); - process_chan_width_distr_dir(Cur, &arch->Chans.chan_y_dist, loc_data); + cur = get_single_child(node, "y", loc_data); + process_chan_width_distr_dir(cur, &arch->Chans.chan_y_dist, loc_data); } /* Takes in node within and loads all the * child type objects. */ static void process_chan_width_distr_dir(pugi::xml_node node, t_chan* chan, const pugiutil::loc_data& loc_data) { - const char* Prop; ReqOpt hasXpeak, hasWidth, hasDc; hasXpeak = hasWidth = hasDc = ReqOpt::OPTIONAL; - Prop = get_attribute(node, "distr", loc_data).value(); - if (strcmp(Prop, "uniform") == 0) { + const char* prop = get_attribute(node, "distr", loc_data).value(); + if (strcmp(prop, "uniform") == 0) { chan->type = e_stat::UNIFORM; - } else if (strcmp(Prop, "gaussian") == 0) { + } else if (strcmp(prop, "gaussian") == 0) { chan->type = e_stat::GAUSSIAN; hasXpeak = hasWidth = hasDc = ReqOpt::REQUIRED; - } else if (strcmp(Prop, "pulse") == 0) { + } else if (strcmp(prop, "pulse") == 0) { chan->type = e_stat::PULSE; hasXpeak = hasWidth = hasDc = ReqOpt::REQUIRED; - } else if (strcmp(Prop, "delta") == 0) { + } else if (strcmp(prop, "delta") == 0) { hasXpeak = hasDc = ReqOpt::REQUIRED; chan->type = e_stat::DELTA; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), - vtr::string_fmt("Unknown property %s for chan_width_distr x\n", Prop).c_str()); + vtr::string_fmt("Unknown property %s for chan_width_distr x\n", prop).c_str()); } chan->peak = get_attribute(node, "peak", loc_data).as_float(ARCH_FPGA_UNDEFINED_VAL); @@ -3057,8 +3035,8 @@ static void process_chan_width_distr_dir(pugi::xml_node node, t_chan* chan, cons } static void process_tiles(pugi::xml_node node, - std::vector& PhysicalTileTypes, - std::vector& LogicalBlockTypes, + std::vector& physical_tile_types, + std::vector& logical_block_types, const t_default_fc_spec& arch_def_fc, t_arch& arch, const pugiutil::loc_data& loc_data, @@ -3067,37 +3045,36 @@ static void process_tiles(pugi::xml_node node, // used to find duplicate tile names std::set tile_type_descriptors; - /* Alloc the type list. Need one additional t_type_descriptors: - * 1: empty pseudo-type - */ + // Alloc the type list. Need one additional t_type_descriptors: + // 1: empty pseudo-type t_physical_tile_type EMPTY_PHYSICAL_TILE_TYPE = get_empty_physical_type(); EMPTY_PHYSICAL_TILE_TYPE.index = 0; - PhysicalTileTypes.push_back(EMPTY_PHYSICAL_TILE_TYPE); + physical_tile_types.push_back(EMPTY_PHYSICAL_TILE_TYPE); - /* Process the types */ - int index = 1; /* Skip over 'empty' type */ + // Process the types + int index = 1; // Skip over 'empty' type - pugi::xml_node CurTileType = node.first_child(); - while (CurTileType) { - check_node(CurTileType, "tile", loc_data); + pugi::xml_node cur_tile_type = node.first_child(); + while (cur_tile_type) { + check_node(cur_tile_type, "tile", loc_data); - t_physical_tile_type PhysicalTileType; + t_physical_tile_type physical_tile_type; - PhysicalTileType.index = index; + physical_tile_type.index = index; - /* Parses the properties fields of the type */ - process_tile_props(CurTileType, &PhysicalTileType, loc_data); + // Parses the properties fields of the type + process_tile_props(cur_tile_type, &physical_tile_type, loc_data); - auto [_, success] = tile_type_descriptors.insert(PhysicalTileType.name); + auto [_, success] = tile_type_descriptors.insert(physical_tile_type.name); if (!success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(CurTileType), - vtr::string_fmt("Duplicate tile descriptor name: '%s'.\n", PhysicalTileType.name.c_str()).c_str()); + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur_tile_type), + vtr::string_fmt("Duplicate tile descriptor name: '%s'.\n", physical_tile_type.name.c_str()).c_str()); } //Warn that gridlocations is no longer supported //TODO: eventually remove try { - expect_child_node_count(CurTileType, "gridlocations", 0, loc_data); + expect_child_node_count(cur_tile_type, "gridlocations", 0, loc_data); } catch (pugiutil::XmlError& e) { std::string msg = e.what(); msg += ". has been replaced by the and tags in the section."; @@ -3105,38 +3082,38 @@ static void process_tiles(pugi::xml_node node, archfpga_throw(e.filename().c_str(), e.line(), msg.c_str()); } - //Load switchblock type and location overrides - pugi::xml_node Cur = get_single_child(CurTileType, "switchblock_locations", loc_data, ReqOpt::OPTIONAL); - process_switch_block_locations(Cur, &PhysicalTileType, arch, loc_data); + // Load switchblock type and location overrides + pugi::xml_node cur = get_single_child(cur_tile_type, "switchblock_locations", loc_data, ReqOpt::OPTIONAL); + process_switch_block_locations(cur, &physical_tile_type, arch, loc_data); - process_sub_tiles(CurTileType, &PhysicalTileType, LogicalBlockTypes, arch.Segments, arch_def_fc, loc_data, num_of_avail_layer); + process_sub_tiles(cur_tile_type, &physical_tile_type, logical_block_types, arch.Segments, arch_def_fc, loc_data, num_of_avail_layer); - /* Type fully read */ + // Type fully read ++index; - /* Push newly created Types to corresponding vectors */ - PhysicalTileTypes.push_back(PhysicalTileType); + // Push newly created Types to corresponding vectors + physical_tile_types.push_back(physical_tile_type); - /* Free this node and get its next sibling node */ - CurTileType = CurTileType.next_sibling(CurTileType.name()); + // Free this node and get its next sibling node + cur_tile_type = cur_tile_type.next_sibling(cur_tile_type.name()); } } -static void mark_IO_types(std::vector& PhysicalTileTypes) { - for (auto& type : PhysicalTileTypes) { +static void mark_IO_types(std::vector& physical_tile_types) { + for (t_physical_tile_type& type : physical_tile_types) { type.is_input_type = false; type.is_output_type = false; - auto equivalent_sites = get_equivalent_sites_set(&type); + std::unordered_set equivalent_sites = get_equivalent_sites_set(&type); - for (const auto& equivalent_site : equivalent_sites) { + for (const t_logical_block_type_ptr& equivalent_site : equivalent_sites) { if (block_type_contains_blif_model(equivalent_site, LogicalModels::MODEL_INPUT)) { type.is_input_type = true; break; } } - for (const auto& equivalent_site : equivalent_sites) { + for (const t_logical_block_type_ptr& equivalent_site : equivalent_sites) { if (block_type_contains_blif_model(equivalent_site, LogicalModels::MODEL_OUTPUT)) { type.is_output_type = true; break; @@ -3146,30 +3123,28 @@ static void mark_IO_types(std::vector& PhysicalTileTypes) } static void process_tile_props(pugi::xml_node node, - t_physical_tile_type* PhysicalTileType, + t_physical_tile_type* physical_tile_type, const pugiutil::loc_data& loc_data) { expect_only_attributes(node, {"name", "width", "height", "area"}, loc_data); - /* Load type name */ - auto Prop = get_attribute(node, "name", loc_data).value(); - PhysicalTileType->name = Prop; + // Load type name + auto prop = get_attribute(node, "name", loc_data).value(); + physical_tile_type->name = prop; - /* Load properties */ - PhysicalTileType->width = get_attribute(node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); - PhysicalTileType->height = get_attribute(node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1); - PhysicalTileType->area = get_attribute(node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); + // Load properties + physical_tile_type->width = get_attribute(node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); + physical_tile_type->height = get_attribute(node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1); + physical_tile_type->area = get_attribute(node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); - if (atof(Prop) < 0) { + if (atof(prop) < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), - vtr::string_fmt("Area for type %s must be non-negative\n", PhysicalTileType->name.c_str()).c_str()); + vtr::string_fmt("Area for type %s must be non-negative\n", physical_tile_type->name.c_str()).c_str()); } } static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, t_sub_tile* sub_tile, const pugiutil::loc_data& loc_data) { - pugi::xml_node Cur; - int num_ports = 0; for (auto port_type : {"input", "output", "clock"}) { num_ports += count_children(Parent, port_type, loc_data, ReqOpt::OPTIONAL); @@ -3183,19 +3158,19 @@ static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, for (auto port_type : {"input", "output", "clock"}) { int port_index_by_type = 0; - Cur = get_first_child(Parent, port_type, loc_data, ReqOpt::OPTIONAL); - while (Cur) { + pugi::xml_node cur = get_first_child(Parent, port_type, loc_data, ReqOpt::OPTIONAL); + while (cur) { t_physical_tile_port port; port.index = port_index; port.absolute_first_pin_index = absolute_first_pin_index; port.port_index_by_type = port_index_by_type; - process_tile_port(Cur, &port, loc_data); + process_tile_port(cur, &port, loc_data); //Check port name duplicates auto [_, subtile_success] = sub_tile_port_names.insert(port.name); if (!subtile_success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate port names in subtile '%s': port '%s'\n", sub_tile->name.c_str(), port.name) .c_str()); @@ -3209,7 +3184,7 @@ static t_pin_counts process_sub_tile_ports(pugi::xml_node Parent, port_index_by_type++; absolute_first_pin_index += port.num_pins; - Cur = Cur.next_sibling(Cur.name()); + cur = cur.next_sibling(cur.name()); } } @@ -3243,26 +3218,25 @@ static void process_tile_port(pugi::xml_node node, expect_only_attributes(node, expected_attributes, loc_data); - const char* Prop; - Prop = get_attribute(node, "name", loc_data).value(); - port->name = vtr::strdup(Prop); + const char* prop = get_attribute(node, "name", loc_data).value(); + port->name = vtr::strdup(prop); - Prop = get_attribute(node, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if (Prop) { - if (Prop == "none"s) { + prop = get_attribute(node, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if (prop) { + if (prop == "none"s) { port->equivalent = PortEquivalence::NONE; - } else if (Prop == "full"s) { + } else if (prop == "full"s) { port->equivalent = PortEquivalence::FULL; - } else if (Prop == "instance"s) { + } else if (prop == "instance"s) { if (node.name() == "output"s) { port->equivalent = PortEquivalence::INSTANCE; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), - vtr::string_fmt("Invalid pin equivalence '%s' for %s port.", Prop, node.name()).c_str()); + vtr::string_fmt("Invalid pin equivalence '%s' for %s port.", prop, node.name()).c_str()); } } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), - vtr::string_fmt("Invalid pin equivalence '%s'.", Prop).c_str()); + vtr::string_fmt("Invalid pin equivalence '%s'.", prop).c_str()); } } port->num_pins = get_attribute(node, "num_pins", loc_data).as_int(0); @@ -3302,11 +3276,9 @@ static void process_tile_port(pugi::xml_node node, static void process_tile_equivalent_sites(pugi::xml_node Parent, t_sub_tile* sub_tile, - t_physical_tile_type* PhysicalTileType, - std::vector& LogicalBlockTypes, + t_physical_tile_type* physical_tile_type, + std::vector& logical_block_types, const pugiutil::loc_data& loc_data) { - pugi::xml_node CurSite; - expect_only_children(Parent, {"site"}, loc_data); if (count_children(Parent, "site", loc_data) < 1) { @@ -3314,46 +3286,46 @@ static void process_tile_equivalent_sites(pugi::xml_node Parent, vtr::string_fmt("There are no sites corresponding to this tile: %s.\n", sub_tile->name.c_str()).c_str()); } - CurSite = Parent.first_child(); - while (CurSite) { - check_node(CurSite, "site", loc_data); + pugi::xml_node cur_site = Parent.first_child(); + while (cur_site) { + check_node(cur_site, "site", loc_data); - expect_only_attributes(CurSite, {"pb_type", "pin_mapping"}, loc_data); - /* Load equivalent site name */ - auto Prop = std::string(get_attribute(CurSite, "pb_type", loc_data).value()); + expect_only_attributes(cur_site, {"pb_type", "pin_mapping"}, loc_data); + // Load equivalent site name + auto prop = std::string(get_attribute(cur_site, "pb_type", loc_data).value()); - auto LogicalBlockType = get_type_by_name(Prop.c_str(), LogicalBlockTypes); + auto logical_block_type = get_type_by_name(prop.c_str(), logical_block_types); - auto pin_mapping = get_attribute(CurSite, "pin_mapping", loc_data, ReqOpt::OPTIONAL).as_string("direct"); + auto pin_mapping = get_attribute(cur_site, "pin_mapping", loc_data, ReqOpt::OPTIONAL).as_string("direct"); if (0 == strcmp(pin_mapping, "custom")) { // Pin mapping between Tile and Pb Type is user-defined - process_equivalent_site_custom_connection(CurSite, sub_tile, PhysicalTileType, LogicalBlockType, Prop, loc_data); + process_equivalent_site_custom_connection(cur_site, sub_tile, physical_tile_type, logical_block_type, prop, loc_data); } else if (0 == strcmp(pin_mapping, "direct")) { - process_equivalent_site_direct_connection(CurSite, sub_tile, PhysicalTileType, LogicalBlockType, loc_data); + process_equivalent_site_direct_connection(cur_site, sub_tile, physical_tile_type, logical_block_type, loc_data); } - if (0 == strcmp(LogicalBlockType->pb_type->name, Prop.c_str())) { - sub_tile->equivalent_sites.push_back(LogicalBlockType); + if (0 == strcmp(logical_block_type->pb_type->name, prop.c_str())) { + sub_tile->equivalent_sites.push_back(logical_block_type); - check_port_direct_mappings(PhysicalTileType, sub_tile, LogicalBlockType); + check_port_direct_mappings(physical_tile_type, sub_tile, logical_block_type); } - CurSite = CurSite.next_sibling(CurSite.name()); + cur_site = cur_site.next_sibling(cur_site.name()); } } static void process_equivalent_site_direct_connection(pugi::xml_node Parent, t_sub_tile* sub_tile, - t_physical_tile_type* PhysicalTileType, - t_logical_block_type* LogicalBlockType, + t_physical_tile_type* physical_tile_type, + const t_logical_block_type* logical_block_type, const pugiutil::loc_data& loc_data) { int num_pins = (int)sub_tile->sub_tile_to_tile_pin_indices.size() / sub_tile->capacity.total(); - if (num_pins != LogicalBlockType->pb_type->num_pins) { + if (num_pins != logical_block_type->pb_type->num_pins) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), vtr::string_fmt("Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", - LogicalBlockType->pb_type->name, + logical_block_type->pb_type->name, sub_tile->name.c_str()) .c_str()); } @@ -3367,17 +3339,15 @@ static void process_equivalent_site_direct_connection(pugi::xml_node Parent, directs_map.insert(logical_pin, physical_pin); } - PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][sub_tile->index] = directs_map; + physical_tile_type->tile_block_pin_directs_map[logical_block_type->index][sub_tile->index] = directs_map; } static void process_equivalent_site_custom_connection(pugi::xml_node Parent, t_sub_tile* sub_tile, - t_physical_tile_type* PhysicalTileType, - t_logical_block_type* LogicalBlockType, + t_physical_tile_type* physical_tile_type, + const t_logical_block_type* logical_block_type, const std::string& site_name, const pugiutil::loc_data& loc_data) { - pugi::xml_node CurDirect; - expect_only_children(Parent, {"direct"}, loc_data); if (count_children(Parent, "direct", loc_data) < 1) { @@ -3389,29 +3359,29 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, vtr::bimap directs_map; - CurDirect = Parent.first_child(); + pugi::xml_node cur_direct = Parent.first_child(); - while (CurDirect) { - check_node(CurDirect, "direct", loc_data); + while (cur_direct) { + check_node(cur_direct, "direct", loc_data); - expect_only_attributes(CurDirect, {"from", "to"}, loc_data); + expect_only_attributes(cur_direct, {"from", "to"}, loc_data); std::string from, to; // `from` attribute is relative to the physical tile pins - from = std::string(get_attribute(CurDirect, "from", loc_data).value()); + from = std::string(get_attribute(cur_direct, "from", loc_data).value()); // `to` attribute is relative to the logical block pins - to = std::string(get_attribute(CurDirect, "to", loc_data).value()); + to = std::string(get_attribute(cur_direct, "to", loc_data).value()); - auto from_pins = process_pin_string(CurDirect, sub_tile, from.c_str(), loc_data); - auto to_pins = process_pin_string(CurDirect, LogicalBlockType, to.c_str(), loc_data); + auto from_pins = process_pin_string(cur_direct, sub_tile, from.c_str(), loc_data); + auto to_pins = process_pin_string(cur_direct, logical_block_type, to.c_str(), loc_data); // Checking that the number of pins is exactly the same if (from_pins.second - from_pins.first != to_pins.second - to_pins.first) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), vtr::string_fmt("The number of pins specified in the direct pin mapping is " "not equivalent for Physical Tile %s and Logical Block %s.\n", - sub_tile->name.c_str(), LogicalBlockType->name.c_str()) + sub_tile->name.c_str(), logical_block_type->name.c_str()) .c_str()); } @@ -3425,46 +3395,45 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), vtr::string_fmt("Duplicate logical pin (%d) to physical pin (%d) mappings found for " "Physical Tile %s and Logical Block %s.\n", - logical_pin.pin, physical_pin.pin, sub_tile->name.c_str(), LogicalBlockType->name.c_str()) + logical_pin.pin, physical_pin.pin, sub_tile->name.c_str(), logical_block_type->name.c_str()) .c_str()); } } - CurDirect = CurDirect.next_sibling(CurDirect.name()); + cur_direct = cur_direct.next_sibling(cur_direct.name()); } - PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][sub_tile->index] = directs_map; + physical_tile_type->tile_block_pin_directs_map[logical_block_type->index][sub_tile->index] = directs_map; } static void process_pin_locations(pugi::xml_node Locations, - t_physical_tile_type* PhysicalTileType, + t_physical_tile_type* physical_tile_type, t_sub_tile* sub_tile, t_pin_locs* pin_locs, const pugiutil::loc_data& loc_data, const int num_of_avail_layer) { - pugi::xml_node Cur; - const char* Prop; - enum e_pin_location_distr distribution; + const char* prop; + e_pin_location_distr distribution; if (Locations) { expect_only_attributes(Locations, {"pattern"}, loc_data); - Prop = get_attribute(Locations, "pattern", loc_data).value(); - if (strcmp(Prop, "spread") == 0) { + prop = get_attribute(Locations, "pattern", loc_data).value(); + if (strcmp(prop, "spread") == 0) { distribution = e_pin_location_distr::SPREAD; - } else if (strcmp(Prop, "perimeter") == 0) { + } else if (strcmp(prop, "perimeter") == 0) { distribution = e_pin_location_distr::PERIMETER; - } else if (strcmp(Prop, "spread_inputs_perimeter_outputs") == 0) { + } else if (strcmp(prop, "spread_inputs_perimeter_outputs") == 0) { distribution = e_pin_location_distr::SPREAD_INPUTS_PERIMETER_OUTPUTS; - } else if (strcmp(Prop, "custom") == 0) { + } else if (strcmp(prop, "custom") == 0) { distribution = e_pin_location_distr::CUSTOM; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - vtr::string_fmt("%s is an invalid pin location pattern.\n", Prop).c_str()); + vtr::string_fmt("%s is an invalid pin location pattern.\n", prop).c_str()); } } else { distribution = e_pin_location_distr::SPREAD; - Prop = "spread"; + prop = "spread"; } if (pin_locs->is_distribution_set()) { @@ -3472,7 +3441,7 @@ static void process_pin_locations(pugi::xml_node Locations, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Sub Tile %s has a different pin location pattern (%s) with respect " "to the sibling sub tiles", - sub_tile->name.c_str(), Prop) + sub_tile->name.c_str(), prop) .c_str()); } } else { @@ -3485,59 +3454,59 @@ static void process_pin_locations(pugi::xml_node Locations, /* Load the pin locations */ if (distribution == e_pin_location_distr::CUSTOM) { expect_only_children(Locations, {"loc"}, loc_data); - Cur = Locations.first_child(); + pugi::xml_node cur = Locations.first_child(); //check for duplications ([0..3][0..type->width-1][0..type->height-1][0..num_of_avail_layer-1]) std::set> seen_sides; - while (Cur) { - check_node(Cur, "loc", loc_data); + while (cur) { + check_node(cur, "loc", loc_data); - expect_only_attributes(Cur, {"side", "xoffset", "yoffset", "layer_offset"}, loc_data); + expect_only_attributes(cur, {"side", "xoffset", "yoffset", "layer_offset"}, loc_data); /* Get offset (height, width, layer) */ - int x_offset = get_attribute(Cur, "xoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); - int y_offset = get_attribute(Cur, "yoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); - int layer_offset = pugiutil::get_attribute(Cur, "layer_offset", loc_data, ReqOpt::OPTIONAL).as_int(0); + int x_offset = get_attribute(cur, "xoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); + int y_offset = get_attribute(cur, "yoffset", loc_data, ReqOpt::OPTIONAL).as_int(0); + int layer_offset = pugiutil::get_attribute(cur, "layer_offset", loc_data, ReqOpt::OPTIONAL).as_int(0); /* Get side */ e_side side = TOP; - Prop = get_attribute(Cur, "side", loc_data).value(); - if (0 == strcmp(Prop, "left")) { + prop = get_attribute(cur, "side", loc_data).value(); + if (0 == strcmp(prop, "left")) { side = LEFT; - } else if (0 == strcmp(Prop, "top")) { + } else if (0 == strcmp(prop, "top")) { side = TOP; - } else if (0 == strcmp(Prop, "right")) { + } else if (0 == strcmp(prop, "right")) { side = RIGHT; - } else if (0 == strcmp(Prop, "bottom")) { + } else if (0 == strcmp(prop, "bottom")) { side = BOTTOM; } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), - vtr::string_fmt("'%s' is not a valid side.\n", Prop).c_str()); + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), + vtr::string_fmt("'%s' is not a valid side.\n", prop).c_str()); } - if ((x_offset < 0) || (x_offset >= PhysicalTileType->width)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + if ((x_offset < 0) || (x_offset >= physical_tile_type->width)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("'%d' is an invalid horizontal offset for type '%s' (must be within [0, %d]).\n", - x_offset, PhysicalTileType->name.c_str(), PhysicalTileType->width - 1) + x_offset, physical_tile_type->name.c_str(), physical_tile_type->width - 1) .c_str()); } - if ((y_offset < 0) || (y_offset >= PhysicalTileType->height)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + if ((y_offset < 0) || (y_offset >= physical_tile_type->height)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("'%d' is an invalid vertical offset for type '%s' (must be within [0, %d]).\n", - y_offset, PhysicalTileType->name.c_str(), PhysicalTileType->height - 1) + y_offset, physical_tile_type->name.c_str(), physical_tile_type->height - 1) .c_str()); } if ((layer_offset < 0) || layer_offset >= num_of_avail_layer) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("'%d' is an invalid layer offset for type '%s' (must be within [0, num_avail_layer-1]).\n", - y_offset, PhysicalTileType->name.c_str(), PhysicalTileType->height - 1) + y_offset, physical_tile_type->name.c_str(), physical_tile_type->height - 1) .c_str()); } - //Check for duplicate side specifications, since the code below silently overwrites if there are duplicates + // Check for duplicate side specifications, since the code below silently overwrites if there are duplicates auto side_offset = std::make_tuple(side, x_offset, y_offset, layer_offset); if (seen_sides.count(side_offset)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate pin location side/offset specification." " Only a single per side/xoffset/yoffset/layer_offset is permitted.\n") .c_str()); @@ -3545,7 +3514,7 @@ static void process_pin_locations(pugi::xml_node Locations, seen_sides.insert(side_offset); /* Go through lists of pins */ - const std::vector Tokens = vtr::StringToken(Cur.child_value()).split(" \t\n"); + const std::vector Tokens = vtr::StringToken(cur.child_value()).split(" \t\n"); int Count = (int)Tokens.size(); if (Count > 0) { for (int pin = 0; pin < Count; ++pin) { @@ -3554,16 +3523,16 @@ static void process_pin_locations(pugi::xml_node Locations, /* Advance through list of pins in this location */ } } - Cur = Cur.next_sibling(Cur.name()); + cur = cur.next_sibling(cur.name()); } - //Verify that all top-level pins have had their locations specified + // Verify that all top-level pins have had their locations specified - //Record all the specified pins, (capacity, port_name, index) + // Record all the specified pins, (capacity, port_name, index) std::map>> port_pins_with_specified_locations; for (int l = 0; l < num_of_avail_layer; ++l) { - for (int w = 0; w < PhysicalTileType->width; ++w) { - for (int h = 0; h < PhysicalTileType->height; ++h) { + for (int w = 0; w < physical_tile_type->width; ++w) { + for (int h = 0; h < physical_tile_type->height; ++h) { for (e_side side : TOTAL_2D_SIDES) { for (const std::string& token : pin_locs->assignments[sub_tile_index][w][h][l][side]) { InstPort inst_port(token); @@ -3657,18 +3626,17 @@ static void process_pin_locations(pugi::xml_node Locations, } static void process_sub_tiles(pugi::xml_node node, - t_physical_tile_type* PhysicalTileType, - std::vector& LogicalBlockTypes, - std::vector& segments, + t_physical_tile_type* physical_tile_type, + std::vector& logical_block_types, + const std::vector& segments, const t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data, const int num_of_avail_layer) { - pugi::xml_node cur_sub_tile; - pugi::xml_node Cur; + pugi::xml_node cur; unsigned long int num_sub_tiles = count_children(node, "sub_tile", loc_data); - unsigned long int width = PhysicalTileType->width; - unsigned long int height = PhysicalTileType->height; + unsigned long int width = physical_tile_type->width; + unsigned long int height = physical_tile_type->height; unsigned long int num_sides = 4; t_pin_locs pin_locs; @@ -3678,7 +3646,7 @@ static void process_sub_tiles(pugi::xml_node node, archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("No sub tile found for the Physical Tile %s.\n" "At least one sub tile is needed to correctly describe the Physical Tile.\n", - PhysicalTileType->name.c_str()) + physical_tile_type->name.c_str()) .c_str()); } @@ -3688,8 +3656,7 @@ static void process_sub_tiles(pugi::xml_node node, // used to assign indices to subtiles int subtile_index = 0; - cur_sub_tile = get_first_child(node, "sub_tile", loc_data); - + pugi::xml_node cur_sub_tile = get_first_child(node, "sub_tile", loc_data); while (cur_sub_tile) { t_sub_tile sub_tile; @@ -3703,54 +3670,53 @@ static void process_sub_tiles(pugi::xml_node node, //Check Sub Tile name duplicates auto [_, success] = sub_tile_names.insert(name); if (!success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate Sub Tile names in tile '%s': Sub Tile'%s'\n", - PhysicalTileType->name.c_str(), name) + physical_tile_type->name.c_str(), name) .c_str()); } sub_tile.name = name; - /* Load properties */ + // Load properties int capacity = get_attribute(cur_sub_tile, "capacity", loc_data, ReqOpt::OPTIONAL).as_int(1); - sub_tile.capacity.set(PhysicalTileType->capacity, PhysicalTileType->capacity + capacity - 1); - PhysicalTileType->capacity += capacity; + sub_tile.capacity.set(physical_tile_type->capacity, physical_tile_type->capacity + capacity - 1); + physical_tile_type->capacity += capacity; - /* Process sub tile port definitions */ + // Process sub tile port definitions const auto pin_counts = process_sub_tile_ports(cur_sub_tile, &sub_tile, loc_data); - /* Map Sub Tile physical pins with the Physical Tile Type physical pins. - * This takes into account the capacity of each sub tiles to add the correct offset. - */ + // Map Sub Tile physical pins with the Physical Tile Type physical pins. + // This takes into account the capacity of each sub tiles to add the correct offset. for (int ipin = 0; ipin < capacity * pin_counts.total(); ipin++) { - sub_tile.sub_tile_to_tile_pin_indices.push_back(PhysicalTileType->num_pins + ipin); + sub_tile.sub_tile_to_tile_pin_indices.push_back(physical_tile_type->num_pins + ipin); } sub_tile.num_phy_pins = pin_counts.total() * capacity; - /* Assign pin counts to the Physical Tile Type */ - PhysicalTileType->num_input_pins += capacity * pin_counts.input; - PhysicalTileType->num_output_pins += capacity * pin_counts.output; - PhysicalTileType->num_clock_pins += capacity * pin_counts.clock; - PhysicalTileType->num_pins += capacity * pin_counts.total(); - PhysicalTileType->num_inst_pins += pin_counts.total(); + // Assign pin counts to the Physical Tile Type + physical_tile_type->num_input_pins += capacity * pin_counts.input; + physical_tile_type->num_output_pins += capacity * pin_counts.output; + physical_tile_type->num_clock_pins += capacity * pin_counts.clock; + physical_tile_type->num_pins += capacity * pin_counts.total(); + physical_tile_type->num_inst_pins += pin_counts.total(); - /* Assign drivers and receivers count to Physical Tile Type */ - PhysicalTileType->num_receivers += capacity * pin_counts.input; - PhysicalTileType->num_drivers += capacity * pin_counts.output; + // Assign drivers and receivers count to Physical Tile Type + physical_tile_type->num_receivers += capacity * pin_counts.input; + physical_tile_type->num_drivers += capacity * pin_counts.output; - Cur = get_single_child(cur_sub_tile, "pinlocations", loc_data, ReqOpt::OPTIONAL); - process_pin_locations(Cur, PhysicalTileType, &sub_tile, &pin_locs, loc_data, num_of_avail_layer); + cur = get_single_child(cur_sub_tile, "pinlocations", loc_data, ReqOpt::OPTIONAL); + process_pin_locations(cur, physical_tile_type, &sub_tile, &pin_locs, loc_data, num_of_avail_layer); - /* Load Fc */ - Cur = get_single_child(cur_sub_tile, "fc", loc_data, ReqOpt::OPTIONAL); - process_fc(Cur, PhysicalTileType, &sub_tile, pin_counts, segments, arch_def_fc, loc_data); + // Load Fc + cur = get_single_child(cur_sub_tile, "fc", loc_data, ReqOpt::OPTIONAL); + process_fc(cur, physical_tile_type, &sub_tile, pin_counts, segments, arch_def_fc, loc_data); - //Load equivalent sites information - Cur = get_single_child(cur_sub_tile, "equivalent_sites", loc_data, ReqOpt::REQUIRED); - process_tile_equivalent_sites(Cur, &sub_tile, PhysicalTileType, LogicalBlockTypes, loc_data); + // Load equivalent sites information + cur = get_single_child(cur_sub_tile, "equivalent_sites", loc_data, ReqOpt::REQUIRED); + process_tile_equivalent_sites(cur, &sub_tile, physical_tile_type, logical_block_types, loc_data); - PhysicalTileType->sub_tiles.push_back(sub_tile); + physical_tile_type->sub_tiles.push_back(sub_tile); subtile_index++; @@ -3758,71 +3724,67 @@ static void process_sub_tiles(pugi::xml_node node, } // Initialize pinloc data structure. - int num_pins = PhysicalTileType->num_pins; - PhysicalTileType->pinloc.resize({width, height, num_sides}, std::vector(num_pins, false)); + int num_pins = physical_tile_type->num_pins; + physical_tile_type->pinloc.resize({width, height, num_sides}, std::vector(num_pins, false)); - setup_pin_classes(PhysicalTileType); - load_pin_loc(Cur, PhysicalTileType, &pin_locs, loc_data, num_of_avail_layer); + setup_pin_classes(physical_tile_type); + load_pin_loc(cur, physical_tile_type, &pin_locs, loc_data, num_of_avail_layer); } /* Takes in node pointing to and loads all the * child type objects. */ static void process_complex_blocks(pugi::xml_node node, - std::vector& LogicalBlockTypes, + std::vector& logical_block_types, const t_arch& arch, const bool timing_enabled, const pugiutil::loc_data& loc_data) { - pugi::xml_node CurBlockType; - pugi::xml_node Cur; - // used to find duplicate pb_types names std::set pb_type_descriptors; - /* Alloc the type list. Need one additional t_type_descriptors: - * 1: empty pseudo-type - */ + // Alloc the type list. Need one additional t_type_descriptors: + // 1: empty pseudo-type t_logical_block_type EMPTY_LOGICAL_BLOCK_TYPE = get_empty_logical_type(); EMPTY_LOGICAL_BLOCK_TYPE.index = 0; - LogicalBlockTypes.push_back(EMPTY_LOGICAL_BLOCK_TYPE); + logical_block_types.push_back(EMPTY_LOGICAL_BLOCK_TYPE); - /* Process the types */ - int index = 1; /* Skip over 'empty' type */ + // Process the types + int index = 1; // Skip over 'empty' type - CurBlockType = node.first_child(); - while (CurBlockType) { + pugi::xml_node cur_block_type = node.first_child(); + while (cur_block_type) { int pb_type_idx = 0; - check_node(CurBlockType, "pb_type", loc_data); + check_node(cur_block_type, "pb_type", loc_data); - t_logical_block_type LogicalBlockType; + t_logical_block_type logical_block_type; - expect_only_attributes(CurBlockType, {"name"}, loc_data); + expect_only_attributes(cur_block_type, {"name"}, loc_data); - /* Load type name */ - auto Prop = get_attribute(CurBlockType, "name", loc_data).value(); - LogicalBlockType.name = Prop; + // Load type name + auto prop = get_attribute(cur_block_type, "name", loc_data).value(); + logical_block_type.name = prop; - auto [_, success] = pb_type_descriptors.insert(LogicalBlockType.name); + auto [_, success] = pb_type_descriptors.insert(logical_block_type.name); if (!success) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(CurBlockType), - vtr::string_fmt("Duplicate pb_type descriptor name: '%s'.\n", LogicalBlockType.name.c_str()).c_str()); + archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur_block_type), + vtr::string_fmt("Duplicate pb_type descriptor name: '%s'.\n", logical_block_type.name.c_str()).c_str()); } - /* Load pb_type info to assign to the Logical Block Type */ - LogicalBlockType.pb_type = new t_pb_type; - LogicalBlockType.pb_type->name = vtr::strdup(LogicalBlockType.name.c_str()); - process_pb_type(CurBlockType, LogicalBlockType.pb_type, nullptr, timing_enabled, arch, loc_data, pb_type_idx); + // Load pb_type info to assign to the Logical Block Type + logical_block_type.pb_type = new t_pb_type; + logical_block_type.pb_type->name = vtr::strdup(logical_block_type.name.c_str()); + process_pb_type(cur_block_type, logical_block_type.pb_type, nullptr, timing_enabled, arch, loc_data, pb_type_idx); - LogicalBlockType.index = index; + logical_block_type.index = index; - /* Type fully read */ + // Type fully read ++index; - /* Push newly created Types to corresponding vectors */ - LogicalBlockTypes.push_back(LogicalBlockType); + // Push newly created Types to corresponding vectors + logical_block_types.push_back(logical_block_type); - /* Free this node and get its next sibling node */ - CurBlockType = CurBlockType.next_sibling(CurBlockType.name()); + // Free this node and get its next sibling node + cur_block_type = cur_block_type.next_sibling(cur_block_type.name()); } } @@ -3834,9 +3796,9 @@ static std::vector process_segments(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { const char* tmp; - std::vector Segs; + std::vector segs; - pugi::xml_node SubElem; + pugi::xml_node sub_elem; pugi::xml_node node; // Count the number of segs specified in the architecture file. @@ -3844,7 +3806,7 @@ static std::vector process_segments(pugi::xml_node parent, // Alloc segment list if (num_segs > 0) { - Segs.resize(num_segs); + segs.resize(num_segs); } // Load the segments. @@ -3858,7 +3820,7 @@ static std::vector process_segments(pugi::xml_node parent, /* Get segment name */ tmp = get_attribute(node, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { - Segs[i].name = std::string(tmp); + segs[i].name = std::string(tmp); } else { /* if swich block is "custom", then you have to provide a name for segment */ if (switchblocklist_required) { @@ -3870,7 +3832,7 @@ static std::vector process_segments(pugi::xml_node parent, ss << "unnamed_segment_" << i; std::string dummy = ss.str(); tmp = dummy.c_str(); - Segs[i].name = std::string(tmp); + segs[i].name = std::string(tmp); } /* Get segment length */ @@ -3878,39 +3840,39 @@ static std::vector process_segments(pugi::xml_node parent, tmp = get_attribute(node, "length", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { if (strcmp(tmp, "longline") == 0) { - Segs[i].longline = true; + segs[i].longline = true; } else { length = vtr::atoi(tmp); } } - Segs[i].length = length; + segs[i].length = length; /* Get the frequency */ - Segs[i].frequency = 1; /* DEFAULT */ + segs[i].frequency = 1; /* DEFAULT */ tmp = get_attribute(node, "freq", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { - Segs[i].frequency = (int)(atof(tmp) * MAX_CHANNEL_WIDTH); + segs[i].frequency = (int)(atof(tmp) * MAX_CHANNEL_WIDTH); } /* Get timing info */ ReqOpt TIMING_ENABLE_REQD = BoolToReqOpt(timing_enabled); - Segs[i].Rmetal = get_attribute(node, "Rmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); - Segs[i].Cmetal = get_attribute(node, "Cmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); + segs[i].Rmetal = get_attribute(node, "Rmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); + segs[i].Cmetal = get_attribute(node, "Cmetal", loc_data, TIMING_ENABLE_REQD).as_float(0); /*Get parallel axis*/ - Segs[i].parallel_axis = e_parallel_axis::BOTH_AXIS; // DEFAULT value if no axis is specified + segs[i].parallel_axis = e_parallel_axis::BOTH_AXIS; // DEFAULT value if no axis is specified tmp = get_attribute(node, "axis", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { if (strcmp(tmp, "x") == 0) { - Segs[i].parallel_axis = e_parallel_axis::X_AXIS; + segs[i].parallel_axis = e_parallel_axis::X_AXIS; x_axis_seg_found = true; } else if (strcmp(tmp, "y") == 0) { - Segs[i].parallel_axis = e_parallel_axis::Y_AXIS; + segs[i].parallel_axis = e_parallel_axis::Y_AXIS; y_axis_seg_found = true; } else if (strcmp(tmp, "z") == 0) { - Segs[i].parallel_axis = e_parallel_axis::Z_AXIS; + segs[i].parallel_axis = e_parallel_axis::Z_AXIS; z_axis_seg_found = true; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), @@ -3927,7 +3889,7 @@ static std::vector process_segments(pugi::xml_node parent, if (tmp) { auto it = std::find(RES_TYPE_STRING.begin(), RES_TYPE_STRING.end(), tmp); if (it != RES_TYPE_STRING.end()) { - Segs[i].res_type = static_cast(std::distance(RES_TYPE_STRING.begin(), it)); + segs[i].res_type = static_cast(std::distance(RES_TYPE_STRING.begin(), it)); } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Unsupported segment res_type: %s\n", tmp).c_str()); @@ -3936,13 +3898,13 @@ static std::vector process_segments(pugi::xml_node parent, /* Get Power info */ /* - * (*Segs)[i].Cmetal_per_m = get_attribute(node, "Cmetal_per_m", false, + * (*segs)[i].Cmetal_per_m = get_attribute(node, "Cmetal_per_m", false, * 0.);*/ // Set of expected subtags (exact subtags are dependent on parameters) std::vector expected_subtags; - if (!Segs[i].longline) { + if (!segs[i].longline) { // Long line doesn't accept or since it assumes full population expected_subtags.emplace_back("sb"); expected_subtags.emplace_back("cb"); @@ -3951,7 +3913,7 @@ static std::vector process_segments(pugi::xml_node parent, // Get the type tmp = get_attribute(node, "type", loc_data).value(); if (0 == strcmp(tmp, "bidir")) { - Segs[i].directionality = BI_DIRECTIONAL; + segs[i].directionality = BI_DIRECTIONAL; //Bidir requires the following tags expected_subtags.emplace_back("wire_switch"); @@ -3959,7 +3921,7 @@ static std::vector process_segments(pugi::xml_node parent, } else if (0 == strcmp(tmp, "unidir")) { - Segs[i].directionality = UNI_DIRECTIONAL; + segs[i].directionality = UNI_DIRECTIONAL; //Unidir requires the following tags expected_subtags.emplace_back("mux"); @@ -3981,134 +3943,134 @@ static std::vector process_segments(pugi::xml_node parent, expect_only_children(node, expected_subtags, loc_data); //Get the switch name for different dice wire and track connections - SubElem = get_single_child(node, "mux_inter_die", loc_data, ReqOpt::OPTIONAL); - tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(""); + sub_elem = get_single_child(node, "mux_inter_die", loc_data, ReqOpt::OPTIONAL); + tmp = get_attribute(sub_elem, "name", loc_data, ReqOpt::OPTIONAL).as_string(""); if (strlen(tmp) != 0) { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("'%s' is not a valid mux name.\n", tmp).c_str()); } - Segs[i].arch_inter_die_switch = switch_idx; + segs[i].arch_inter_die_switch = switch_idx; } /* Get the wire and opin switches, or mux switch if unidir */ - if (UNI_DIRECTIONAL == Segs[i].directionality) { + if (UNI_DIRECTIONAL == segs[i].directionality) { //Get the switch name for same die wire and track connections - SubElem = get_single_child(node, "mux", loc_data, ReqOpt::OPTIONAL); - tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + sub_elem = get_single_child(node, "mux", loc_data, ReqOpt::OPTIONAL); + tmp = get_attribute(sub_elem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); //check if tag is defined in the architecture, otherwise we should look for and if (tmp) { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("'%s' is not a valid mux name.\n", tmp).c_str()); } /* Unidir muxes must have the same switch * for wire and opin fanin since there is * really only the mux in unidir. */ - Segs[i].arch_wire_switch = switch_idx; - Segs[i].arch_opin_switch = switch_idx; + segs[i].arch_wire_switch = switch_idx; + segs[i].arch_opin_switch = switch_idx; } else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file - SubElem = get_single_child(node, "mux_inc", loc_data, ReqOpt::OPTIONAL); - tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + sub_elem = get_single_child(node, "mux_inc", loc_data, ReqOpt::OPTIONAL); + tmp = get_attribute(sub_elem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (!tmp) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified").c_str()); } else { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("'%s' is not a valid mux name.\n", tmp).c_str()); } /* Unidir muxes must have the same switch * for wire and opin fanin since there is * really only the mux in unidir. */ - Segs[i].arch_wire_switch = switch_idx; - Segs[i].arch_opin_switch = switch_idx; + segs[i].arch_wire_switch = switch_idx; + segs[i].arch_opin_switch = switch_idx; } - SubElem = get_single_child(node, "mux_dec", loc_data, ReqOpt::OPTIONAL); - tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + sub_elem = get_single_child(node, "mux_dec", loc_data, ReqOpt::OPTIONAL); + tmp = get_attribute(sub_elem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (!tmp) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified").c_str()); } else { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("'%s' is not a valid mux name.\n", tmp).c_str()); } /* Unidir muxes must have the same switch * for wire and opin fanin since there is * really only the mux in unidir. */ - Segs[i].arch_wire_switch_dec = switch_idx; - Segs[i].arch_opin_switch_dec = switch_idx; + segs[i].arch_wire_switch_dec = switch_idx; + segs[i].arch_opin_switch_dec = switch_idx; } } } else { - VTR_ASSERT(BI_DIRECTIONAL == Segs[i].directionality); - SubElem = get_single_child(node, "wire_switch", loc_data); - tmp = get_attribute(SubElem, "name", loc_data).value(); + VTR_ASSERT(BI_DIRECTIONAL == segs[i].directionality); + sub_elem = get_single_child(node, "wire_switch", loc_data); + tmp = get_attribute(sub_elem, "name", loc_data).value(); /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("'%s' is not a valid wire_switch name.\n", tmp).c_str()); } - Segs[i].arch_wire_switch = switch_idx; - SubElem = get_single_child(node, "opin_switch", loc_data); - tmp = get_attribute(SubElem, "name", loc_data).value(); + segs[i].arch_wire_switch = switch_idx; + sub_elem = get_single_child(node, "opin_switch", loc_data); + tmp = get_attribute(sub_elem, "name", loc_data).value(); /* Match names */ switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("'%s' is not a valid opin_switch name.\n", tmp).c_str()); } - Segs[i].arch_opin_switch = switch_idx; + segs[i].arch_opin_switch = switch_idx; } /* Setup the CB list if they give one, otherwise use full */ - Segs[i].cb.resize(length); + segs[i].cb.resize(length); for (int j = 0; j < length; ++j) { - Segs[i].cb[j] = true; + segs[i].cb[j] = true; } - SubElem = get_single_child(node, "cb", loc_data, ReqOpt::OPTIONAL); - if (SubElem) { - process_cb_sb(SubElem, Segs[i].cb, loc_data); + sub_elem = get_single_child(node, "cb", loc_data, ReqOpt::OPTIONAL); + if (sub_elem) { + process_cb_sb(sub_elem, segs[i].cb, loc_data); } /* Setup the SB list if they give one, otherwise use full */ - Segs[i].sb.resize(length + 1); + segs[i].sb.resize(length + 1); for (int j = 0; j < (length + 1); ++j) { - Segs[i].sb[j] = true; + segs[i].sb[j] = true; } - SubElem = get_single_child(node, "sb", loc_data, ReqOpt::OPTIONAL); - if (SubElem) { - process_cb_sb(SubElem, Segs[i].sb, loc_data); + sub_elem = get_single_child(node, "sb", loc_data, ReqOpt::OPTIONAL); + if (sub_elem) { + process_cb_sb(sub_elem, segs[i].sb, loc_data); } // Setup the bend list if they give one, otherwise use default if (length > 1) { - Segs[i].is_bend = false; - SubElem = get_single_child(node, "bend", loc_data, ReqOpt::OPTIONAL); - if (SubElem) { - process_bend(SubElem, Segs[i], (length - 1), loc_data); + segs[i].is_bend = false; + sub_elem = get_single_child(node, "bend", loc_data, ReqOpt::OPTIONAL); + if (sub_elem) { + process_bend(sub_elem, segs[i], (length - 1), loc_data); } } - // Store the index of this segment in Segs vector - Segs[i].seg_index = i; + // Store the index of this segment in segs vector + segs[i].seg_index = i; // Get next node node = node.next_sibling(node.name()); } @@ -4124,7 +4086,7 @@ static std::vector process_segments(pugi::xml_node parent, vtr::string_fmt("At least one segment along Z axis needs to get specified if for 3D architectures.").c_str()); } - return Segs; + return segs; } static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int len, const pugiutil::loc_data& loc_data) { @@ -4197,21 +4159,21 @@ static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int } static void calculate_custom_sb_locations(const pugiutil::loc_data& loc_data, - const pugi::xml_node& SubElem, + const pugi::xml_node& sub_elem, const int grid_width, const int grid_height, t_switchblock_inf& sb) { - auto startx_attr = get_attribute(SubElem, "startx", loc_data, ReqOpt::OPTIONAL); - auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL); + auto startx_attr = get_attribute(sub_elem, "startx", loc_data, ReqOpt::OPTIONAL); + auto endx_attr = get_attribute(sub_elem, "endx", loc_data, ReqOpt::OPTIONAL); - auto starty_attr = get_attribute(SubElem, "starty", loc_data, ReqOpt::OPTIONAL); - auto endy_attr = get_attribute(SubElem, "endy", loc_data, ReqOpt::OPTIONAL); + auto starty_attr = get_attribute(sub_elem, "starty", loc_data, ReqOpt::OPTIONAL); + auto endy_attr = get_attribute(sub_elem, "endy", loc_data, ReqOpt::OPTIONAL); - auto repeatx_attr = get_attribute(SubElem, "repeatx", loc_data, ReqOpt::OPTIONAL); - auto repeaty_attr = get_attribute(SubElem, "repeaty", loc_data, ReqOpt::OPTIONAL); + auto repeatx_attr = get_attribute(sub_elem, "repeatx", loc_data, ReqOpt::OPTIONAL); + auto repeaty_attr = get_attribute(sub_elem, "repeaty", loc_data, ReqOpt::OPTIONAL); - auto incrx_attr = get_attribute(SubElem, "incrx", loc_data, ReqOpt::OPTIONAL); - auto incry_attr = get_attribute(SubElem, "incry", loc_data, ReqOpt::OPTIONAL); + auto incrx_attr = get_attribute(sub_elem, "incrx", loc_data, ReqOpt::OPTIONAL); + auto incry_attr = get_attribute(sub_elem, "incry", loc_data, ReqOpt::OPTIONAL); // parse the values from the architecture file and fill out SB region information vtr::FormulaParser p; @@ -4237,9 +4199,6 @@ static void calculate_custom_sb_locations(const pugiutil::loc_data& loc_data, * See vpr/SRC/route/build_switchblocks.c for a detailed description of this * switch block format */ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data) { - pugi::xml_node node; - pugi::xml_node SubElem; - const char* tmp; /* get the number of switchblocks */ const int num_switchblocks = count_children(Parent, "switchblock", loc_data); @@ -4253,14 +4212,14 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug } } - /* read-in all switchblock data */ - node = get_first_child(Parent, "switchblock", loc_data); + // read-in all switchblock data + pugi::xml_node node = get_first_child(Parent, "switchblock", loc_data); for (int i_sb = 0; i_sb < num_switchblocks; i_sb++) { /* use a temp variable which will be assigned to switchblocks later */ t_switchblock_inf sb; - /* get name */ - tmp = get_attribute(node, "name", loc_data).as_string(nullptr); + // get name + const char* tmp = get_attribute(node, "name", loc_data).as_string(nullptr); if (tmp) { sb.name = tmp; } @@ -4279,12 +4238,12 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug } // get the switchblock location - SubElem = get_single_child(node, "switchblock_location", loc_data); - tmp = get_attribute(SubElem, "type", loc_data).as_string(nullptr); + pugi::xml_node sub_elem = get_single_child(node, "switchblock_location", loc_data); + tmp = get_attribute(sub_elem, "type", loc_data).as_string(nullptr); if (tmp) { auto sb_location_iter = SB_LOCATION_STRING_MAP.find(tmp); if (sb_location_iter == SB_LOCATION_STRING_MAP.end()) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("unrecognized switchblock location: %s\n", tmp).c_str()); } else { sb.location = sb_location_iter->second; @@ -4294,10 +4253,10 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug // Get the switchblock coordinate only if sb.location is set to E_XY_SPECIFIED if (sb.location == e_sb_location::E_XY_SPECIFIED) { if (arch->device_layout == "auto") { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("Specifying SB locations for auto layout devices are not supported yet!\n").c_str()); } - expect_only_attributes(SubElem, + expect_only_attributes(sub_elem, {"x", "y", "type", "startx", "endx", "repeatx", "incrx", "starty", "endy", "repeaty", "incry"}, @@ -4307,12 +4266,12 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug int grid_height = arch->grid_layouts.at(layout_index).height; // Absolute location that this SB must be applied to, -1 if not specified - sb.specified_loc.x = get_attribute(SubElem, "x", loc_data, ReqOpt::OPTIONAL).as_int(ARCH_FPGA_UNDEFINED_VAL); - sb.specified_loc.y = get_attribute(SubElem, "y", loc_data, ReqOpt::OPTIONAL).as_int(ARCH_FPGA_UNDEFINED_VAL); + sb.specified_loc.x = get_attribute(sub_elem, "x", loc_data, ReqOpt::OPTIONAL).as_int(ARCH_FPGA_UNDEFINED_VAL); + sb.specified_loc.y = get_attribute(sub_elem, "y", loc_data, ReqOpt::OPTIONAL).as_int(ARCH_FPGA_UNDEFINED_VAL); // Check if the absolute value is within the device grid width and height if (sb.specified_loc.x >= grid_width || sb.specified_loc.y >= grid_height) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(sub_elem), vtr::string_fmt("Location (%d,%d) is not valid within the grid! grid dimensions are: (%d,%d)\n", sb.specified_loc.x, sb.specified_loc.y, grid_width, grid_height) .c_str()); @@ -4322,13 +4281,13 @@ static void process_switch_blocks(pugi::xml_node Parent, t_arch* arch, const pug // we have to parse the region specification and apply the SB pattern to all the locations fall into the specified // region based on device width and height. if (sb.specified_loc.x == ARCH_FPGA_UNDEFINED_VAL && sb.specified_loc.y == ARCH_FPGA_UNDEFINED_VAL) { - calculate_custom_sb_locations(loc_data, SubElem, grid_width, grid_height, sb); + calculate_custom_sb_locations(loc_data, sub_elem, grid_width, grid_height, sb); } } // get switchblock permutation functions - SubElem = get_first_child(node, "switchfuncs", loc_data); - read_sb_switchfuncs(SubElem, sb, loc_data); + sub_elem = get_first_child(node, "switchfuncs", loc_data); + read_sb_switchfuncs(sub_elem, sb, loc_data); read_sb_wireconns(arch->switches, node, sb, loc_data); @@ -4407,12 +4366,8 @@ static void process_cb_sb(pugi::xml_node node, std::vector& list, const pu static std::vector process_switches(pugi::xml_node Parent, const bool timing_enabled, const pugiutil::loc_data& loc_data) { - const char* type_name; - const char* switch_name; ReqOpt TIMING_ENABLE_REQD = BoolToReqOpt(timing_enabled); - pugi::xml_node node; - /* Count the children and check they are switches */ int n_switches = count_children(Parent, "switch", loc_data); std::vector switches; @@ -4422,12 +4377,12 @@ static std::vector process_switches(pugi::xml_node Parent, switches.resize(n_switches); } - /* Load the switches. */ - node = get_first_child(Parent, "switch", loc_data); + // Load the switches. + pugi::xml_node node = get_first_child(Parent, "switch", loc_data); for (int i = 0; i < n_switches; ++i) { t_arch_switch_inf& arch_switch = switches[i]; - switch_name = get_attribute(node, "name", loc_data).value(); + const char* switch_name = get_attribute(node, "name", loc_data).value(); /* Check if the switch has conflicts with any reserved names */ if (0 == strcmp(switch_name, VPR_DELAYLESS_SWITCH_NAME)) { @@ -4437,9 +4392,9 @@ static std::vector process_switches(pugi::xml_node Parent, .c_str()); } - type_name = get_attribute(node, "type", loc_data).value(); + const char* type_name = get_attribute(node, "type", loc_data).value(); - /* Check for switch name collisions */ + // Check for switch name collisions for (int j = 0; j < i; ++j) { if (0 == strcmp(switches[j].name.c_str(), switch_name)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), @@ -4588,7 +4543,7 @@ static void process_switch_tdel(pugi::xml_node node, const bool timing_enabled, int num_inputs = get_attribute(Tdel_child, "num_inputs", loc_data).as_int(0); float Tdel_value = get_attribute(Tdel_child, "delay", loc_data).as_float(0.); - if (seen_fanins.count(num_inputs)) { + if (seen_fanins.contains(num_inputs)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Tdel_child), vtr::string_fmt("Tdel node specified num_inputs (%d) that has already been specified by another Tdel node", num_inputs).c_str()); } else { @@ -4918,7 +4873,7 @@ static void process_clock_switch_points(pugi::xml_node parent, static void process_clock_routing(pugi::xml_node parent, std::vector& clock_connections, const std::vector& switches, - pugiutil::loc_data& loc_data) { + const pugiutil::loc_data& loc_data) { std::vector expected_attributes = {"from", "to", "switch", "fc_val", "locationx", "locationy"}; pugi::xml_node clock_routing_parent = get_single_child(parent, "clock_routing", loc_data); @@ -4959,21 +4914,19 @@ static void process_clock_routing(pugi::xml_node parent, static void process_power(pugi::xml_node parent, t_power_arch* power_arch, const pugiutil::loc_data& loc_data) { - pugi::xml_node Cur; - - /* Get the local interconnect capacitances */ + // Get the local interconnect capacitances power_arch->local_interc_factor = 0.5; - Cur = get_single_child(parent, "local_interconnect", loc_data, ReqOpt::OPTIONAL); - if (Cur) { - power_arch->C_wire_local = get_attribute(Cur, "C_wire", loc_data, ReqOpt::OPTIONAL).as_float(0.); - power_arch->local_interc_factor = get_attribute(Cur, "factor", loc_data, ReqOpt::OPTIONAL).as_float(0.5); + pugi::xml_node cur = get_single_child(parent, "local_interconnect", loc_data, ReqOpt::OPTIONAL); + if (cur) { + power_arch->C_wire_local = get_attribute(cur, "C_wire", loc_data, ReqOpt::OPTIONAL).as_float(0.); + power_arch->local_interc_factor = get_attribute(cur, "factor", loc_data, ReqOpt::OPTIONAL).as_float(0.5); } /* Get logical effort factor */ power_arch->logical_effort_factor = 4.0; - Cur = get_single_child(parent, "buffers", loc_data, ReqOpt::OPTIONAL); - if (Cur) { - power_arch->logical_effort_factor = get_attribute(Cur, + cur = get_single_child(parent, "buffers", loc_data, ReqOpt::OPTIONAL); + if (cur) { + power_arch->logical_effort_factor = get_attribute(cur, "logical_effort_factor", loc_data) .as_float(0); ; @@ -4981,34 +4934,34 @@ static void process_power(pugi::xml_node parent, /* Get SRAM Size */ power_arch->transistors_per_SRAM_bit = 6.0; - Cur = get_single_child(parent, "sram", loc_data, ReqOpt::OPTIONAL); - if (Cur) { - power_arch->transistors_per_SRAM_bit = get_attribute(Cur, + cur = get_single_child(parent, "sram", loc_data, ReqOpt::OPTIONAL); + if (cur) { + power_arch->transistors_per_SRAM_bit = get_attribute(cur, "transistors_per_bit", loc_data) .as_float(0); } /* Get Mux transistor size */ power_arch->mux_transistor_size = 1.0; - Cur = get_single_child(parent, "mux_transistor_size", loc_data, ReqOpt::OPTIONAL); - if (Cur) { - power_arch->mux_transistor_size = get_attribute(Cur, + cur = get_single_child(parent, "mux_transistor_size", loc_data, ReqOpt::OPTIONAL); + if (cur) { + power_arch->mux_transistor_size = get_attribute(cur, "mux_transistor_size", loc_data) .as_float(0); } /* Get FF size */ power_arch->FF_size = 1.0; - Cur = get_single_child(parent, "FF_size", loc_data, ReqOpt::OPTIONAL); - if (Cur) { - power_arch->FF_size = get_attribute(Cur, "FF_size", loc_data).as_float(0); + cur = get_single_child(parent, "FF_size", loc_data, ReqOpt::OPTIONAL); + if (cur) { + power_arch->FF_size = get_attribute(cur, "FF_size", loc_data).as_float(0); } /* Get LUT transistor size */ power_arch->LUT_transistor_size = 1.0; - Cur = get_single_child(parent, "LUT_transistor_size", loc_data, ReqOpt::OPTIONAL); - if (Cur) { - power_arch->LUT_transistor_size = get_attribute(Cur, + cur = get_single_child(parent, "LUT_transistor_size", loc_data, ReqOpt::OPTIONAL); + if (cur) { + power_arch->LUT_transistor_size = get_attribute(cur, "LUT_transistor_size", loc_data) .as_float(0); } @@ -5016,17 +4969,14 @@ static void process_power(pugi::xml_node parent, /* Get the clock architecture */ static void process_clocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data) { - pugi::xml_node node; - const char* tmp; - int num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); clocks.resize(num_global_clocks, t_clock_network()); /* Load the clock info. */ - node = get_first_child(Parent, "clock", loc_data); + pugi::xml_node node = get_first_child(Parent, "clock", loc_data); for (int i = 0; i < num_global_clocks; ++i) { - tmp = get_attribute(node, "buffer_size", loc_data).value(); + const char* tmp = get_attribute(node, "buffer_size", loc_data).value(); if (strcmp(tmp, "auto") == 0) { clocks[i].autosize_buffer = true; } else { diff --git a/libs/libarchfpga/src/read_xml_arch_file.h b/libs/libarchfpga/src/read_xml_arch_file.h index 8da7a398c4..b092fb6138 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.h +++ b/libs/libarchfpga/src/read_xml_arch_file.h @@ -12,11 +12,11 @@ extern "C" { #define EMPTY_TYPE_INDEX 0 /* function declarations */ -void xml_read_arch(const char* ArchFile, +void xml_read_arch(const char* arch_file, const bool timing_enabled, t_arch* arch, - std::vector& PhysicalTileTypes, - std::vector& LogicalBlockTypes); + std::vector& physical_tile_types, + std::vector& logical_block_types); #ifdef __cplusplus } From 34bb767f03938eaff899e7b08a63fb7538deeebb Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 15:46:15 -0400 Subject: [PATCH 05/14] use std:string for storing pin names in t_pin_to_pin_annotations --- libs/libarchfpga/src/arch_check.cpp | 16 +-- libs/libarchfpga/src/arch_util.cpp | 59 +++------- libs/libarchfpga/src/arch_util.h | 2 +- libs/libarchfpga/src/echo_arch.cpp | 10 +- libs/libarchfpga/src/physical_types.h | 11 +- .../src/read_fpga_interchange_arch.cpp | 16 +-- libs/libarchfpga/src/read_xml_arch_file.cpp | 48 ++++---- libs/libvtrutil/src/vtr_token.cpp | 8 +- libs/libvtrutil/src/vtr_token.h | 6 +- libs/libvtrutil/src/vtr_util.cpp | 12 +- libs/libvtrutil/src/vtr_util.h | 16 +-- vpr/src/pack/pb_type_graph.cpp | 2 +- vpr/src/pack/pb_type_graph.h | 2 +- vpr/src/pack/pb_type_graph_annotations.cpp | 109 ++++++++++-------- 14 files changed, 148 insertions(+), 169 deletions(-) diff --git a/libs/libarchfpga/src/arch_check.cpp b/libs/libarchfpga/src/arch_check.cpp index ac33f234f2..620d15bbd3 100644 --- a/libs/libarchfpga/src/arch_check.cpp +++ b/libs/libarchfpga/src/arch_check.cpp @@ -163,11 +163,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) { //Check that any combinational delays specified match the 'combinational_sinks_ports' in the model - if (annotation.clock) { + if (!annotation.clock.empty()) { //Sequential annotation, check that the clock on the specified port matches the model - //Annotations always put the pin in the input_pins field - VTR_ASSERT(annotation.input_pins); + // Annotations always put the pin in the input_pins field + VTR_ASSERT(!annotation.input_pins.empty()); for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) { InstPort annot_port(input_pin); for (const std::string& clock : vtr::StringToken(annotation.clock).split(" \t\n")) { @@ -207,15 +207,15 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } } - } else if (annotation.input_pins && annotation.output_pins) { - //Combinational annotation - VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock"); + } else if (!annotation.input_pins.empty() && !annotation.output_pins.empty()) { + // Combinational annotation + VTR_ASSERT_MSG(annotation.clock.empty(), "Combinational annotations should have no clock"); for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) { InstPort annot_in(input_pin); for (const std::string& output_pin : vtr::StringToken(annotation.output_pins).split(" \t\n")) { InstPort annot_out(output_pin); - //Find the input model port + // Find the input model port const t_model_ports* model_port = nullptr; for (const t_model_ports* port = model.inputs; port != nullptr; port = port->next) { if (port->name == annot_in.port_name()) { @@ -230,7 +230,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar annot_in.port_name().c_str(), annot_in.instance_name().c_str()); } - //Check that the output port is listed in the model's combinational sinks + // Check that the output port is listed in the model's combinational sinks auto b = model_port->combinational_sink_ports.begin(); auto e = model_port->combinational_sink_ports.end(); auto iter = std::find(b, e, annot_out.port_name()); diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 126cc87e95..bf7d22844b 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -320,11 +320,6 @@ static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->modes[i].interconnect[j].output_string); vtr::free(pb_type->modes[i].interconnect[j].name); - for (t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) { - vtr::free(annotation.clock); - vtr::free(annotation.input_pins); - vtr::free(annotation.output_pins); - } pb_type->modes[i].interconnect[j].annotations.clear(); delete pb_type->modes[i].interconnect[j].interconnect_power; } @@ -333,12 +328,6 @@ static void free_pb_type(t_pb_type* pb_type) { } delete[] pb_type->modes; - - for (t_pin_to_pin_annotation& annotation : pb_type->annotations) { - vtr::free(annotation.input_pins); - vtr::free(annotation.output_pins); - vtr::free(annotation.clock); - } pb_type->annotations.clear(); delete pb_type->pb_type_power; @@ -439,13 +428,11 @@ std::unordered_set get_equivalent_sites_set(t_physical } void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, - char* new_name, + std::string_view new_name, t_pb_type* copy) { - char* dot; - VTR_ASSERT(pb_type->blif_model != nullptr); - copy->name = vtr::strdup(new_name); + copy->name = vtr::strdup(new_name.data()); copy->blif_model = vtr::strdup(pb_type->blif_model); copy->class_type = pb_type->class_type; copy->depth = pb_type->depth; @@ -482,8 +469,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) { copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO; copy->ports[i].port_power->buffer_type = POWER_BUFFER_TYPE_AUTO; - } else if (copy->pb_type_power->estimation_method - == POWER_METHOD_SPECIFY_SIZES) { + } else if (copy->pb_type_power->estimation_method == POWER_METHOD_SPECIFY_SIZES) { copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_IGNORED; copy->ports[i].port_power->buffer_type = POWER_BUFFER_TYPE_NONE; } @@ -492,20 +478,18 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, size_t num_annotations = pb_type->annotations.size(); copy->annotations.resize(num_annotations); for (size_t i = 0; i < num_annotations; i++) { - copy->annotations[i].clock = vtr::strdup(pb_type->annotations[i].clock); - dot = strstr(pb_type->annotations[i].input_pins, "."); - copy->annotations[i].input_pins = (char*)vtr::malloc(sizeof(char) * (strlen(new_name) + strlen(dot) + 1)); - copy->annotations[i].input_pins[0] = '\0'; - strcat(copy->annotations[i].input_pins, new_name); - strcat(copy->annotations[i].input_pins, dot); - if (pb_type->annotations[i].output_pins != nullptr) { - dot = strstr(pb_type->annotations[i].output_pins, "."); - copy->annotations[i].output_pins = (char*)vtr::malloc(sizeof(char) * (strlen(new_name) + strlen(dot) + 1)); - copy->annotations[i].output_pins[0] = '\0'; - strcat(copy->annotations[i].output_pins, new_name); - strcat(copy->annotations[i].output_pins, dot); + copy->annotations[i].clock = pb_type->annotations[i].clock; + + auto dot_pos = pb_type->annotations[i].input_pins.find('.'); + VTR_ASSERT_MSG(dot_pos != std::string::npos, "Expected '.' in input_pins"); + copy->annotations[i].input_pins = std::string(new_name) + pb_type->annotations[i].input_pins.substr(dot_pos); + + if (!pb_type->annotations[i].output_pins.empty()) { + dot_pos = pb_type->annotations[i].output_pins.find('.'); + VTR_ASSERT_MSG(dot_pos != std::string::npos, "Expected '.' in output_pins"); + copy->annotations[i].output_pins = std::string(new_name) + pb_type->annotations[i].output_pins.substr(dot_pos); } else { - copy->annotations[i].output_pins = nullptr; + copy->annotations[i].output_pins.clear(); } copy->annotations[i].line_num = pb_type->annotations[i].line_num; copy->annotations[i].format = pb_type->annotations[i].format; @@ -572,9 +556,9 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { size_t num_annotations = lut_pb_type->annotations.size(); lut_pb_type->modes[0].interconnect[0].annotations.resize(num_annotations); for (size_t i = 0; i < num_annotations; i++) { - lut_pb_type->modes[0].interconnect[0].annotations[i].clock = vtr::strdup(lut_pb_type->annotations[i].clock); - lut_pb_type->modes[0].interconnect[0].annotations[i].input_pins = vtr::strdup(lut_pb_type->annotations[i].input_pins); - lut_pb_type->modes[0].interconnect[0].annotations[i].output_pins = vtr::strdup(lut_pb_type->annotations[i].output_pins); + lut_pb_type->modes[0].interconnect[0].annotations[i].clock = lut_pb_type->annotations[i].clock; + lut_pb_type->modes[0].interconnect[0].annotations[i].input_pins = lut_pb_type->annotations[i].input_pins; + lut_pb_type->modes[0].interconnect[0].annotations[i].output_pins =lut_pb_type->annotations[i].output_pins; lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num; lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format; lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type; @@ -592,12 +576,6 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].pb_type_children = new t_pb_type[1]; alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name, lut_pb_type->modes[1].pb_type_children); - /* moved annotations to child so delete old annotations */ - for (size_t i = 0; i < num_annotations; i++) { - vtr::free(lut_pb_type->annotations[i].input_pins); - vtr::free(lut_pb_type->annotations[i].output_pins); - vtr::free(lut_pb_type->annotations[i].clock); - } lut_pb_type->annotations.clear(); lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1; lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1]; @@ -962,8 +940,7 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, for (i_port = 0; i_port < parent_pb_type->num_ports; i_port++) { if (parent_pb_type->ports[i_port].is_clock) { - if (strcmp(parent_pb_type->ports[i_port].name, annotation->clock) - == 0) { + if (parent_pb_type->ports[i_port].name == annotation->clock) { clock_valid = true; break; } diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index 41994287ff..e0f714aaa0 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -69,7 +69,7 @@ t_logical_block_type get_empty_logical_type(const char* name = EMPTY_BLOCK_NAME) std::unordered_set get_equivalent_sites_set(t_physical_tile_type_ptr type); void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, - char* new_name, + std::string_view new_name, t_pb_type* copy); void ProcessLutClass(t_pb_type* lut_pb_type); diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 2105b8fd7e..983c37d1c0 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -401,8 +401,8 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c pb_type->modes[i].interconnect[j].output_string); for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) { fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(), - annotation.input_pins, - annotation.output_pins, + annotation.input_pins.c_str(), + annotation.output_pins.c_str(), annotation.format, annotation.annotation_entries[0].second.c_str()); } @@ -428,9 +428,9 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c && pb_type_model_name != LogicalModels::MODEL_OUTPUT) { for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) { fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs.c_str(), - annotation.clock, - annotation.input_pins, - annotation.output_pins, + annotation.clock.c_str(), + annotation.input_pins.c_str(), + annotation.output_pins.c_str(), annotation.format, annotation.annotation_entries[0].second.c_str()); } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 84c8009b98..64df9dd4ba 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1076,18 +1076,13 @@ struct t_pin_to_pin_annotation { e_pin_to_pin_annotation_type type; e_pin_to_pin_annotation_format format; - char* input_pins; - char* output_pins; - char* clock; + std::string input_pins; + std::string output_pins; + std::string clock; int line_num; /* used to report what line number this annotation is found in architecture file */ t_pin_to_pin_annotation() noexcept { - annotation_entries = std::vector>(); - input_pins = nullptr; - output_pins = nullptr; - clock = nullptr; - line_num = 0; type = (e_pin_to_pin_annotation_type)0; format = (e_pin_to_pin_annotation_format)0; diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index d382428d01..848c2773be 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -242,28 +242,28 @@ static t_port get_generic_port(t_arch* arch, } /** @brief Returns true if a given port name exists in the given complex block */ -static bool block_port_exists(t_pb_type* pb_type, std::string port_name) { +static bool block_port_exists(t_pb_type* pb_type, std::string_view port_name) { for (int iport = 0; iport < pb_type->num_ports; iport++) { const t_port port = pb_type->ports[iport]; - if (std::string(port.name) == port_name) + if (port.name == port_name) return true; } return false; } -/** @brief Returns a pack pattern given it's name, input and output strings */ -static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) { +/** @brief Returns a pack pattern given its name, input and output strings */ +static t_pin_to_pin_annotation get_pack_pattern(std::string_view pp_name, std::string_view input, std::string_view output) { t_pin_to_pin_annotation pp; pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT; - pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name}); - pp.input_pins = vtr::strdup(input.c_str()); - pp.output_pins = vtr::strdup(output.c_str()); + pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name.data()}); + pp.input_pins = input; + pp.output_pins = output; - pp.clock = nullptr; + pp.clock.clear(); return pp; } diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 2352642229..9d78831c9f 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -333,7 +333,7 @@ static std::vector process_directs(pugi::xml_node Parent, static void process_clock_metal_layers(pugi::xml_node parent, std::unordered_map& metal_layers, - pugiutil::loc_data& loc_data); + const pugiutil::loc_data& loc_data); static void process_clock_networks(pugi::xml_node parent, std::vector& clock_networks, const std::vector& switches, @@ -1026,10 +1026,10 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, i++; } prop = get_attribute(Parent, "in_port", loc_data).value(); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "out_port", loc_data).value(); - annotation->output_pins = vtr::strdup(prop); + annotation->output_pins = prop; } else if (0 == strcmp(Parent.name(), "delay_matrix")) { annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; @@ -1046,10 +1046,10 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, i++; prop = get_attribute(Parent, "in_port", loc_data).value(); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "out_port", loc_data).value(); - annotation->output_pins = vtr::strdup(prop); + annotation->output_pins = prop; } else if (0 == strcmp(Parent.name(), "C_constant")) { annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; @@ -1059,11 +1059,11 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, i++; prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->output_pins = vtr::strdup(prop); - VTR_ASSERT(annotation->output_pins != nullptr || annotation->input_pins != nullptr); + annotation->output_pins = prop; + VTR_ASSERT(!annotation->output_pins.empty() || !annotation->input_pins.empty()); } else if (0 == strcmp(Parent.name(), "C_matrix")) { annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; @@ -1072,11 +1072,11 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, i++; prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - annotation->output_pins = vtr::strdup(prop); - VTR_ASSERT(annotation->output_pins != nullptr || annotation->input_pins != nullptr); + annotation->output_pins = prop; + VTR_ASSERT(!annotation->output_pins.empty() || !annotation->input_pins.empty()); } else if (0 == strcmp(Parent.name(), "T_setup")) { annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; @@ -1085,10 +1085,10 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_TSETUP, prop}; i++; prop = get_attribute(Parent, "port", loc_data).value(); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "clock", loc_data).value(); - annotation->clock = vtr::strdup(prop); + annotation->clock = prop; primitives_annotation_clock_match(annotation, parent_pb_type); @@ -1118,10 +1118,10 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, } prop = get_attribute(Parent, "port", loc_data).value(); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "clock", loc_data).value(); - annotation->clock = vtr::strdup(prop); + annotation->clock = prop; primitives_annotation_clock_match(annotation, parent_pb_type); @@ -1133,10 +1133,10 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, i++; prop = get_attribute(Parent, "port", loc_data).value(); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "clock", loc_data).value(); - annotation->clock = vtr::strdup(prop); + annotation->clock = prop; primitives_annotation_clock_match(annotation, parent_pb_type); @@ -1148,10 +1148,10 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent, i++; prop = get_attribute(Parent, "in_port", loc_data).value(); - annotation->input_pins = vtr::strdup(prop); + annotation->input_pins = prop; prop = get_attribute(Parent, "out_port", loc_data).value(); - annotation->output_pins = vtr::strdup(prop); + annotation->output_pins = prop; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), @@ -2490,7 +2490,7 @@ static void process_model_ports(pugi::xml_node port_group, t_model& model, std:: vtr::string_fmt("Model port is missing a name").c_str()); } - if (port_names.count(model_port->name)) { + if (port_names.contains(model_port->name)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(port), vtr::string_fmt("Duplicate model port named '%s'", model_port->name).c_str()); } @@ -3505,7 +3505,7 @@ static void process_pin_locations(pugi::xml_node Locations, // Check for duplicate side specifications, since the code below silently overwrites if there are duplicates auto side_offset = std::make_tuple(side, x_offset, y_offset, layer_offset); - if (seen_sides.count(side_offset)) { + if (seen_sides.contains(side_offset)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur), vtr::string_fmt("Duplicate pin location side/offset specification." " Only a single per side/xoffset/yoffset/layer_offset is permitted.\n") @@ -3609,7 +3609,7 @@ static void process_pin_locations(pugi::xml_node Locations, for (int iinst = sub_tile->capacity.low; iinst < sub_tile->capacity.high; ++iinst) { for (const t_physical_tile_port& port : sub_tile->ports) { for (int ipin = 0; ipin < port.num_pins; ++ipin) { - if (!port_pins_with_specified_locations[iinst][port.name].count(ipin)) { + if (!port_pins_with_specified_locations[iinst][port.name].contains(ipin)) { //Missing archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", @@ -3887,7 +3887,7 @@ static std::vector process_segments(pugi::xml_node parent, tmp = get_attribute(node, "res_type", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { - auto it = std::find(RES_TYPE_STRING.begin(), RES_TYPE_STRING.end(), tmp); + auto it = std::ranges::find(RES_TYPE_STRING, tmp); if (it != RES_TYPE_STRING.end()) { segs[i].res_type = static_cast(std::distance(RES_TYPE_STRING.begin(), it)); } else { @@ -4644,7 +4644,7 @@ static std::vector process_directs(pugi::xml_node Parent, static void process_clock_metal_layers(pugi::xml_node parent, std::unordered_map& metal_layers, - pugiutil::loc_data& loc_data) { + const pugiutil::loc_data& loc_data) { std::vector expected_attributes = {"name", "Rmetal", "Cmetal"}; std::vector expected_children = {"metal_layer"}; diff --git a/libs/libvtrutil/src/vtr_token.cpp b/libs/libvtrutil/src/vtr_token.cpp index 816755df7f..c77d607959 100644 --- a/libs/libvtrutil/src/vtr_token.cpp +++ b/libs/libvtrutil/src/vtr_token.cpp @@ -87,11 +87,11 @@ static e_token_type get_token_type_from_char(e_token_type cur_token_type, char c } } -void my_atof_2D(float** matrix, const int max_i, const int max_j, const char* instring) { +void my_atof_2D(float** matrix, const int max_i, const int max_j, std::string_view instring) { int i, j; char *cur, *cur2, *copy, *final; - copy = vtr::strdup(instring); + copy = vtr::strdup(instring.data()); final = copy; while (*final != '\0') { final++; @@ -127,9 +127,9 @@ void my_atof_2D(float** matrix, const int max_i, const int max_j, const char* in free(copy); } -bool check_my_atof_2D(const int max_i, const int max_j, const char* instring, int* num_entries) { +bool check_my_atof_2D(const int max_i, const int max_j, std::string_view instring, int* num_entries) { /* Check if max_i * max_j matches number of entries in instring */ - const char* cur = instring; + const char* cur = instring.data(); bool in_str = false; int entry_count = 0; diff --git a/libs/libvtrutil/src/vtr_token.h b/libs/libvtrutil/src/vtr_token.h index 7933cccd69..1c87c6e37c 100644 --- a/libs/libvtrutil/src/vtr_token.h +++ b/libs/libvtrutil/src/vtr_token.h @@ -44,11 +44,11 @@ class Tokens { }; /// @brief Returns a 2D array representing the atof result of all the input string entries seperated by whitespace -void my_atof_2D(float** matrix, const int max_i, const int max_j, const char* instring); +void my_atof_2D(float** matrix, const int max_i, const int max_j, std::string_view instring); /** - * @brief Checks if the number of entries (separated by whitespace) matches the the expected number (max_i * max_j) + * @brief Checks if the number of entries (separated by whitespace) matches the expected number (max_i * max_j) * * can be used before calling my_atof_2D */ -bool check_my_atof_2D(const int max_i, const int max_j, const char* instring, int* num_entries); +bool check_my_atof_2D(const int max_i, const int max_j, std::string_view instring, int* num_entries); diff --git a/libs/libvtrutil/src/vtr_util.cpp b/libs/libvtrutil/src/vtr_util.cpp index c7223207cc..180faeff64 100644 --- a/libs/libvtrutil/src/vtr_util.cpp +++ b/libs/libvtrutil/src/vtr_util.cpp @@ -138,11 +138,11 @@ char* strdup(const char* str) { * and/or correct 'unexpected' behaviour of the standard c-functions */ template -T atoT(const std::string& value, std::string_view type_name) { +T atoT(std::string_view value, std::string_view type_name) { //The c version of atof doesn't catch errors. // //This version uses stringstream to detect conversion errors - std::istringstream ss(value); + std::istringstream ss(value.data()); T val; ss >> val; @@ -157,19 +157,19 @@ T atoT(const std::string& value, std::string_view type_name) { return val; } -int atoi(const std::string& value) { +int atoi(std::string_view value) { return atoT(value, "int"); } -double atod(const std::string& value) { +double atod(std::string_view value) { return atoT(value, "double"); } -float atof(const std::string& value) { +float atof(std::string_view value) { return atoT(value, "float"); } -unsigned atou(const std::string& value) { +unsigned atou(std::string_view value) { return atoT(value, "unsigned int"); } diff --git a/libs/libvtrutil/src/vtr_util.h b/libs/libvtrutil/src/vtr_util.h index 43f2c16f3e..e5e09900b3 100644 --- a/libs/libvtrutil/src/vtr_util.h +++ b/libs/libvtrutil/src/vtr_util.h @@ -115,34 +115,34 @@ char* getline(char*& _lineptr, FILE* _stream); /** * @brief Legacy c-style function replacements. * - * Typically these add extra error checking + * Typically, these add extra error checking * and/or correct 'unexpected' behaviour of the standard c-functions */ -int atoi(const std::string& value); +int atoi(std::string_view value); /** * @brief Legacy c-style function replacements. * - * Typically these add extra error checking + * Typically, these add extra error checking * and/or correct 'unexpected' behaviour of the standard c-functions */ -unsigned atou(const std::string& value); +unsigned atou(std::string_view value); /** * @brief Legacy c-style function replacements. * - * Typically these add extra error checking + * Typically, these add extra error checking * and/or correct 'unexpected' behaviour of the standard c-functions */ -float atof(const std::string& value); +float atof(std::string_view value); /** * @brief Legacy c-style function replacements. * - * Typically these add extra error checking + * Typically, these add extra error checking * and/or correct 'unexpected' behaviour of the standard c-functions */ -double atod(const std::string& value); +double atod(std::string_view value); /** * @brief File utilities diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index f515e2b41c..85f9730585 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -952,7 +952,7 @@ static void store_pin_sinks_edge_id(t_pb_graph_node* pb_graph_node) { t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num, const t_pb_graph_node* pb_graph_parent_node, t_pb_graph_node** pb_graph_children_nodes, - const char* port_string, + std::string_view port_string, int** num_ptrs, int* num_sets, const bool is_input_to_interc, diff --git a/vpr/src/pack/pb_type_graph.h b/vpr/src/pack/pb_type_graph.h index 00e7af6777..fb0bf83536 100644 --- a/vpr/src/pack/pb_type_graph.h +++ b/vpr/src/pack/pb_type_graph.h @@ -23,7 +23,7 @@ void free_pb_graph_edges(); t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num, const t_pb_graph_node* pb_graph_parent_node, t_pb_graph_node** pb_graph_children_nodes, - const char* port_string, + std::string_view port_string, int** num_ptrs, int* num_sets, const bool is_input_to_interc, diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index f60a6bf912..3986792c71 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -5,7 +5,6 @@ #include #include #include -#include #include #include "arch_util.h" @@ -19,23 +18,28 @@ #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value); +static void load_pack_pattern_annotations(const int line_num, + t_pb_graph_node* pb_graph_node, + const int mode, + std::string_view annot_in_pins, + std::string_view annot_out_pins, + std::string_view value); static void load_delay_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, - const enum e_pin_to_pin_annotation_format input_format, - const enum e_pin_to_pin_delay_annotations delay_type, - const char* annot_in_pins, - const char* annot_out_pins, - const char* clock, - const char* value); + const e_pin_to_pin_annotation_format input_format, + const e_pin_to_pin_delay_annotations delay_type, + std::string_view annot_in_pins, + std::string_view annot_out_pins, + std::string_view clock, + std::string_view value); static void inferr_unspecified_pb_graph_node_delays(t_pb_graph_node* pb_graph_node); static void inferr_unspecified_pb_graph_pin_delays(t_pb_graph_pin* pb_graph_pin); static void inferr_unspecified_pb_graph_edge_delays(t_pb_graph_edge* pb_graph_pin); -static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, const char* clock, int line_num); +static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, std::string_view clock, int line_num); void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { const t_pb_type* pb_type = pb_graph_node->pb_type; @@ -52,11 +56,11 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { || key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP || key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { load_delay_annotations(annotation.line_num, pb_graph_node, UNDEFINED, - annotation.format, (enum e_pin_to_pin_delay_annotations)key, + annotation.format, (e_pin_to_pin_delay_annotations)key, annotation.input_pins, annotation.output_pins, annotation.clock, - val.c_str()); + val); } else { VTR_ASSERT(false); } @@ -78,11 +82,11 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { || key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { load_delay_annotations(annotation.line_num, pb_graph_node, i, annotation.format, - (enum e_pin_to_pin_delay_annotations)key, + (e_pin_to_pin_delay_annotations)key, annotation.input_pins, annotation.output_pins, annotation.clock, - val.c_str()); + val); } else { VTR_ASSERT(false); } @@ -118,23 +122,27 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { /* * Add the pattern name to the pack_pattern field for each pb_graph_edge that is used in a pack pattern */ -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value) { - int i, j, m, n, iedge; - t_pb_graph_pin ***in_port, ***out_port; +static void load_pack_pattern_annotations(const int line_num, + t_pb_graph_node* pb_graph_node, + const int mode, + std::string_view annot_in_pins, + std::string_view annot_out_pins, + std::string_view value) { int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; t_pb_graph_node** children = nullptr; children = pb_graph_node->child_pb_graph_nodes[mode]; - in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, - annot_in_pins, &num_in_ptrs, &num_in_sets, false, false); - out_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, - annot_out_pins, &num_out_ptrs, &num_out_sets, false, false); + t_pb_graph_pin*** in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, + annot_in_pins, &num_in_ptrs, &num_in_sets, false, false); + t_pb_graph_pin*** out_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, + annot_out_pins, &num_out_ptrs, &num_out_sets, false, false); /* Discover edge then annotate edge with name of pack pattern */ - for (i = 0; i < num_in_sets; i++) { - for (j = 0; j < num_in_ptrs[i]; j++) { - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { + for (int i = 0; i < num_in_sets; i++) { + for (int j = 0; j < num_in_ptrs[i]; j++) { + for (int m = 0; m < num_out_sets; m++) { + for (int n = 0; n < num_out_ptrs[m]; n++) { + int iedge; for (iedge = 0; iedge < in_port[i][j]->num_output_edges; iedge++) { if (in_port[i][j]->output_edges[iedge]->output_pins[0] == out_port[m][n]) { break; @@ -145,7 +153,7 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p if (iedge != in_port[i][j]->num_output_edges) { in_port[i][j]->output_edges[iedge]->num_pack_patterns++; in_port[i][j]->output_edges[iedge]->pack_pattern_names.resize(in_port[i][j]->output_edges[iedge]->num_pack_patterns); - in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value.c_str(); // TODO: convert to std::string + in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value.data(); // TODO: convert to std::string } } } @@ -153,14 +161,14 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p } if (in_port != nullptr) { - for (i = 0; i < num_in_sets; i++) { + for (int i = 0; i < num_in_sets; i++) { delete[] in_port[i]; } delete[] in_port; delete[] num_in_ptrs; } if (out_port != nullptr) { - for (i = 0; i < num_out_sets; i++) { + for (int i = 0; i < num_out_sets; i++) { delete[] out_port[i]; } delete[] out_port; @@ -171,13 +179,13 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p static void load_delay_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, - const enum e_pin_to_pin_annotation_format input_format, - const enum e_pin_to_pin_delay_annotations delay_type, - const char* annot_in_pins, - const char* annot_out_pins, - const char* clock, - const char* value) { - int i, j, k, m, n, p, iedge; + const e_pin_to_pin_annotation_format input_format, + const e_pin_to_pin_delay_annotations delay_type, + std::string_view annot_in_pins, + std::string_view annot_out_pins, + std::string_view clock, + std::string_view value) { + int i, j, k; t_pb_graph_pin ***in_port, ***out_port; int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; float** delay_matrix; @@ -300,8 +308,8 @@ static void load_delay_annotations(const int line_num, //Fast look-up for out pin membership std::set out_pins; - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { + for (int m = 0; m < num_out_sets; m++) { + for (int n = 0; n < num_out_ptrs[m]; n++) { out_pins.insert(out_port[m][n]); } } @@ -313,10 +321,10 @@ static void load_delay_annotations(const int line_num, k = 0; for (i = 0; i < num_in_sets; i++) { for (j = 0; j < num_in_ptrs[i]; j++) { - p = 0; - for (iedge = 0; iedge < in_port[i][j]->num_output_edges; iedge++) { + int p = 0; + for (int iedge = 0; iedge < in_port[i][j]->num_output_edges; iedge++) { t_pb_graph_edge* pb_edge = in_port[i][j]->output_edges[iedge]; - if (out_pins.count(pb_edge->output_pins[0])) { + if (out_pins.contains(pb_edge->output_pins[0])) { if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_MAX) { if (pb_edge->delay_max != 0) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, @@ -347,7 +355,7 @@ static void load_delay_annotations(const int line_num, for (k = 0; k < src_pin->num_pin_timing; ++k) { t_pb_graph_pin* sink_pin = src_pin->pin_timing[k]; auto edge_pair = std::make_pair(src_pin, sink_pin); - VTR_ASSERT_MSG(!existing_edges.count(edge_pair), "No duplicates"); + VTR_ASSERT_MSG(!existing_edges.contains(edge_pair), "No duplicates"); existing_edges.emplace(src_pin, sink_pin); } } @@ -358,11 +366,11 @@ static void load_delay_annotations(const int line_num, for (i = 0; i < num_in_sets; i++) { for (j = 0; j < num_in_ptrs[i]; j++) { t_pb_graph_pin* src_pin = in_port[i][j]; - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { + for (int m = 0; m < num_out_sets; m++) { + for (int n = 0; n < num_out_ptrs[m]; n++) { t_pb_graph_pin* sink_pin = out_port[m][n]; auto edge = std::make_pair(src_pin, sink_pin); - if (!existing_edges.count(edge)) { + if (!existing_edges.contains(edge)) { new_edges.insert(edge); } } @@ -396,9 +404,9 @@ static void load_delay_annotations(const int line_num, } //Apply the timing annotation (now that all pin_timing for it exist) - p = 0; - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { + int p = 0; + for (int m = 0; m < num_out_sets; m++) { + for (int n = 0; n < num_out_ptrs[m]; n++) { if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_MAX) { if (src_pin->num_pin_timing_del_max_annotated >= src_pin->num_pin_timing) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, @@ -546,14 +554,13 @@ static void inferr_unspecified_pb_graph_edge_delays(t_pb_graph_edge* pb_graph_ed } } -static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, const char* clock, int line_num) { +static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, std::string_view clock, int line_num) { t_pb_graph_pin* clock_pin = nullptr; for (int iport = 0; iport < gnode->num_clock_ports; ++iport) { VTR_ASSERT(gnode->num_clock_pins[iport] == 1); - if (strcmp(clock, gnode->clock_pins[iport][0].port->name) == 0) { - VTR_ASSERT(!clock_pin); - if (clock_pin) { + if (clock == gnode->clock_pins[iport][0].port->name) { + if (clock_pin != nullptr) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, "Found duplicate clock-pin match"); } @@ -561,7 +568,7 @@ static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, const char* clock, } } - if (!clock_pin) { + if (clock_pin != nullptr) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, "Failed to find associated clock pin"); } From 07a0f34825fd206a5fef9ae02c2a3666e05d9d6a Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 16:35:21 -0400 Subject: [PATCH 06/14] std::string for t_arch:architecture_id --- libs/libarchfpga/src/arch_util.cpp | 2 +- libs/libarchfpga/src/physical_types.h | 6 +++--- libs/libarchfpga/src/read_fpga_interchange_arch.cpp | 2 +- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index bf7d22844b..affae5f647 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -162,7 +162,7 @@ void free_arch(t_arch* arch) { vtr::release_memory(arch->directs); - vtr::free(arch->architecture_id); + vtr::release_memory(arch->architecture_id); delete (arch->noc); } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 64df9dd4ba..fd8c309b66 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1966,7 +1966,7 @@ struct t_arch { std::vector interned_strings; /// Secure hash digest of the architecture file to uniquely identify this architecture - char* architecture_id; + std::string architecture_id; // Options for tileable routing architectures // These are used for an alternative, tilable, rr-graph generator that can produce @@ -2001,12 +2001,12 @@ struct t_arch { int sub_fs; /// Connecting type for pass tracks in each switch block - enum e_switch_block_type sb_sub_type; + e_switch_block_type sb_sub_type; // End of tileable architecture options t_chan_width_dist Chans; - enum e_switch_block_type sb_type; + e_switch_block_type sb_type; std::vector switchblocks; float R_minW_nmos; float R_minW_pmos; diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 848c2773be..852715b4a2 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -2529,7 +2529,7 @@ void FPGAInterchangeReadArch(const char* FPGAInterchangeDeviceFile, auto device_reader = message_reader.getRoot(); - arch->architecture_id = vtr::strdup(vtr::secure_digest_file(FPGAInterchangeDeviceFile).c_str()); + arch->architecture_id = vtr::secure_digest_file(FPGAInterchangeDeviceFile); ArchReader reader(arch, device_reader, FPGAInterchangeDeviceFile, PhysicalTileTypes, LogicalBlockTypes); reader.read_arch(); diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 9d78831c9f..c73b35606e 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -409,7 +409,7 @@ void xml_read_arch(const char* arch_file, } //Create a unique identifier for this architecture file based on it's contents - arch->architecture_id = vtr::strdup(vtr::secure_digest_file(arch_file).c_str()); + arch->architecture_id = vtr::secure_digest_file(arch_file); // Parse the file try { From a2418f36db937069ac5ba299987c3127bd21f5bc Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 16:35:52 -0400 Subject: [PATCH 07/14] std::string for input/output_string in t_interconnect --- libs/libarchfpga/src/arch_util.cpp | 123 +++++------------- libs/libarchfpga/src/echo_arch.cpp | 4 +- libs/libarchfpga/src/physical_types.h | 6 +- .../src/read_fpga_interchange_arch.cpp | 52 ++++---- libs/libarchfpga/src/read_xml_arch_file.cpp | 4 +- vpr/src/pack/pb_type_graph.cpp | 20 +-- 6 files changed, 72 insertions(+), 137 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index affae5f647..2cb345ad52 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -316,8 +316,6 @@ static void free_pb_type(t_pb_type* pb_type) { delete[] pb_type->modes[i].pb_type_children; vtr::free(pb_type->modes[i].name); for (int j = 0; j < pb_type->modes[i].num_interconnect; ++j) { - vtr::free(pb_type->modes[i].interconnect[j].input_string); - vtr::free(pb_type->modes[i].interconnect[j].output_string); vtr::free(pb_type->modes[i].interconnect[j].name); pb_type->modes[i].interconnect[j].annotations.clear(); @@ -500,14 +498,14 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, /* populate special lut class */ void ProcessLutClass(t_pb_type* lut_pb_type) { - char* default_name; + std::string default_name; t_port* in_port; t_port* out_port; if (strcmp(lut_pb_type->name, "lut") != 0) { - default_name = vtr::strdup("lut"); + default_name = "lut"; } else { - default_name = vtr::strdup("lut_child"); + default_name = "lut_child"; } lut_pb_type->num_modes = 2; @@ -540,14 +538,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s", lut_pb_type->name); lut_pb_type->modes[0].interconnect[0].type = COMPLETE_INTERC; - lut_pb_type->modes[0].interconnect[0].input_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(in_port->name) + 2, - sizeof(char)); - sprintf(lut_pb_type->modes[0].interconnect[0].input_string, "%s.%s", - lut_pb_type->name, in_port->name); - lut_pb_type->modes[0].interconnect[0].output_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(out_port->name) + 2, - sizeof(char)); - sprintf(lut_pb_type->modes[0].interconnect[0].output_string, "%s.%s", - lut_pb_type->name, out_port->name); + lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name); + lut_pb_type->modes[0].interconnect[0].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name); lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0; lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0]; @@ -592,13 +584,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s", lut_pb_type->name); lut_pb_type->modes[1].interconnect[0].type = DIRECT_INTERC; - lut_pb_type->modes[1].interconnect[0].input_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(in_port->name) + 2, - sizeof(char)); - sprintf(lut_pb_type->modes[1].interconnect[0].input_string, "%s.%s", - lut_pb_type->name, in_port->name); - lut_pb_type->modes[1].interconnect[0].output_string = (char*)vtr::calloc(strlen(default_name) + strlen(in_port->name) + 2, sizeof(char)); - sprintf(lut_pb_type->modes[1].interconnect[0].output_string, "%s.%s", - default_name, in_port->name); + lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt(lut_pb_type->name, in_port->name); + lut_pb_type->modes[1].interconnect[0].output_string = default_name + '.' + in_port->name; lut_pb_type->modes[1].interconnect[0].infer_annotations = true; lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1; @@ -610,22 +597,14 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->name); lut_pb_type->modes[1].interconnect[1].type = DIRECT_INTERC; - lut_pb_type->modes[1].interconnect[1].input_string = (char*)vtr::calloc(strlen(default_name) + strlen(out_port->name) + 4, sizeof(char)); - sprintf(lut_pb_type->modes[1].interconnect[1].input_string, "%s.%s", - default_name, out_port->name); - lut_pb_type->modes[1].interconnect[1].output_string = (char*)vtr::calloc(strlen(lut_pb_type->name) + strlen(out_port->name) - + strlen(in_port->name) + 2, - sizeof(char)); - sprintf(lut_pb_type->modes[1].interconnect[1].output_string, "%s.%s", - lut_pb_type->name, out_port->name); + lut_pb_type->modes[1].interconnect[1].input_string = vtr::string_fmt("%s.%s", default_name, out_port->name); + lut_pb_type->modes[1].interconnect[1].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name); lut_pb_type->modes[1].interconnect[1].infer_annotations = true; lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1; lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1]; lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power(); - free(default_name); - free(lut_pb_type->blif_model); lut_pb_type->blif_model = nullptr; lut_pb_type->model_id = LogicalModelId::INVALID(); @@ -633,23 +612,20 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { /* populate special memory class */ void ProcessMemoryClass(t_pb_type* mem_pb_type) { - char* default_name; - char *input_name, *input_port_name, *output_name, *output_port_name; - int i, j, i_inter, num_pb; - + std::string default_name; if (strcmp(mem_pb_type->name, "memory_slice") != 0) { - default_name = vtr::strdup("memory_slice"); + default_name = "memory_slice"; } else { - default_name = vtr::strdup("memory_slice_1bit"); + default_name = "memory_slice_1bit"; } mem_pb_type->modes = new t_mode[1]; - mem_pb_type->modes[0].name = vtr::strdup(default_name); + mem_pb_type->modes[0].name = vtr::strdup(default_name.data()); mem_pb_type->modes[0].parent_pb_type = mem_pb_type; mem_pb_type->modes[0].index = 0; mem_pb_type->modes[0].mode_power = new t_mode_power(); - num_pb = ARCH_FPGA_UNDEFINED_VAL; - for (i = 0; i < mem_pb_type->num_ports; i++) { + int num_pb = ARCH_FPGA_UNDEFINED_VAL; + for (int i = 0; i < mem_pb_type->num_ports; i++) { if (mem_pb_type->ports[i].port_class != nullptr && strstr(mem_pb_type->ports[i].port_class, "data") == mem_pb_type->ports[i].port_class) { @@ -684,18 +660,19 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { VTR_ASSERT_MSG(mem_pb_type->modes[0].num_interconnect > 0, error_msg.c_str()); mem_pb_type->modes[0].interconnect = new t_interconnect[mem_pb_type->modes[0].num_interconnect]; - for (i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) { + for (int i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) { mem_pb_type->modes[0].interconnect[i].parent_mode_index = 0; mem_pb_type->modes[0].interconnect[i].parent_mode = &mem_pb_type->modes[0]; } /* Process interconnect */ - i_inter = 0; - for (i = 0; i < mem_pb_type->num_ports; i++) { + int i_inter = 0; + for (int i = 0; i < mem_pb_type->num_ports; i++) { mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC; - input_port_name = mem_pb_type->ports[i].name; - output_port_name = mem_pb_type->ports[i].name; + char* input_port_name = mem_pb_type->ports[i].name; + char* output_port_name = mem_pb_type->ports[i].name; + std::string_view input_name, output_name; if (mem_pb_type->ports[i].type == IN_PORT) { input_name = mem_pb_type->name; output_name = default_name; @@ -717,39 +694,21 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1; mem_pb_type->modes[0].pb_type_children[0].num_input_pins -= (mem_pb_type->ports[i].num_pins - 1); - mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name) - + 2, - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string, - "%s.%s", input_name, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name) + strlen(output_port_name) - + 2 * (6 + num_pb / 10), - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string, - "%s[%d:0].%s", output_name, num_pb - 1, - output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:0].%s", output_name, num_pb - 1, output_port_name); } else { /* force data pins to be one bit wide and update stats */ mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1; mem_pb_type->modes[0].pb_type_children[0].num_output_pins -= (mem_pb_type->ports[i].num_pins - 1); - - mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name) - + 2 * (6 + num_pb / 10), - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string, - "%s[%d:0].%s", input_name, num_pb - 1, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name) + strlen(output_port_name) - + 2, - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string, - "%s.%s", output_name, output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:0].%s", input_name, num_pb - 1, input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name); } /* Allocate interconnect power structures */ mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power(); i_inter++; } else { - for (j = 0; j < num_pb; j++) { + for (int j = 0; j < num_pb; j++) { /* Anything that is not data must be an input */ mem_pb_type->modes[0].interconnect[i_inter].name = (char*)vtr::calloc(i_inter / 10 + j / 10 + 10, sizeof(char)); @@ -759,30 +718,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { if (mem_pb_type->ports[i].type == IN_PORT) { mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC; - mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name) - + 2, - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string, - "%s.%s", input_name, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name) - + strlen(output_port_name) - + 2 * (6 + num_pb / 10), - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string, - "%s[%d:%d].%s", output_name, j, j, - output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:%d].%s", output_name, j, j, output_port_name); } else { mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC; - mem_pb_type->modes[0].interconnect[i_inter].input_string = (char*)vtr::calloc(strlen(input_name) + strlen(input_port_name) - + 2 * (6 + num_pb / 10), - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string, - "%s[%d:%d].%s", input_name, j, j, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = (char*)vtr::calloc(strlen(output_name) - + strlen(output_port_name) + 2, - sizeof(char)); - sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string, - "%s.%s", output_name, output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:%d].%s", input_name, j, j, input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name); } /* Allocate interconnect power structures */ @@ -793,8 +734,6 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { } mem_pb_type->modes[0].num_interconnect = i_inter; - - free(default_name); } e_power_estimation_method power_method_inherited(e_power_estimation_method parent_power_method) { @@ -950,7 +889,7 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, if (!clock_valid) { archfpga_throw(get_arch_file_name(), annotation->line_num, "Clock '%s' does not match any clock defined in pb_type '%s'.\n", - annotation->clock, parent_pb_type->name); + annotation->clock.c_str(), parent_pb_type->name); } } diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 983c37d1c0..91e31b4f99 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -397,8 +397,8 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs.c_str(), pb_type->modes[i].interconnect[j].type, - pb_type->modes[i].interconnect[j].input_string, - pb_type->modes[i].interconnect[j].output_string); + pb_type->modes[i].interconnect[j].input_string.c_str(), + pb_type->modes[i].interconnect[j].output_string.c_str()); for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) { fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(), annotation.input_pins.c_str(), diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index fd8c309b66..17afd5d375 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1108,8 +1108,8 @@ struct t_interconnect { e_interconnect type; char* name; - char* input_string; - char* output_string; + std::string input_string; + std::string output_string; std::vector annotations; bool infer_annotations; @@ -1127,8 +1127,6 @@ struct t_interconnect { t_interconnect() { type = (e_interconnect)0; name = nullptr; - input_string = nullptr; - output_string = nullptr; infer_annotations = false; line_num = 0; parent_mode_index = 0; diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 852715b4a2..b2bb9167de 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -1216,8 +1216,8 @@ struct ArchReader { ostr = std::string(pb_type->name) + ".in[" + std::to_string(j) + "]"; name = istr + "_to_" + ostr; - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; ic->name = vtr::strdup(name.c_str()); } @@ -1231,8 +1231,8 @@ struct ArchReader { ostr = std::string(parent->name) + "." + lut_bel.output_pin; name = istr + "_to_" + ostr; - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; ic->name = vtr::strdup(name.c_str()); } } @@ -1267,14 +1267,12 @@ struct ArchReader { mode->interconnect = new t_interconnect[mode->num_interconnect]; t_interconnect* ic = &mode->interconnect[0]; - std::string istr, ostr, name; + std::string istr = std::string(pb_type->name) + ".in"; + std::string ostr = std::string(pb_type->name) + ".out"; + std::string name = "passthrough"; - istr = std::string(pb_type->name) + ".in"; - ostr = std::string(pb_type->name) + ".out"; - name = "passthrough"; - - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; ic->name = vtr::strdup(name.c_str()); ic->type = COMPLETE_INTERC; @@ -1329,8 +1327,8 @@ struct ArchReader { ostr = std::string(lut->name) + ".in"; name = istr + "_to_" + ostr; - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; ic->name = vtr::strdup(name.c_str()); // Output @@ -1343,8 +1341,8 @@ struct ArchReader { ostr = std::string(pb_type->name) + ".out"; name = istr + "_to_" + ostr; - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; ic->name = vtr::strdup(name.c_str()); } @@ -1458,15 +1456,15 @@ struct ArchReader { o_ic->type = DIRECT_INTERC; o_ic->parent_mode_index = 0; o_ic->parent_mode = omode; - o_ic->input_string = vtr::strdup(opad_istr.c_str()); - o_ic->output_string = vtr::strdup(opad_ostr.c_str()); + o_ic->input_string = opad_istr; + o_ic->output_string = opad_ostr; i_ic->name = vtr::strdup(i_ic_name.c_str()); i_ic->type = DIRECT_INTERC; i_ic->parent_mode_index = 0; i_ic->parent_mode = imode; - i_ic->input_string = vtr::strdup(ipad_istr.c_str()); - i_ic->output_string = vtr::strdup(ipad_ostr.c_str()); + i_ic->input_string = ipad_istr.c_str(); + i_ic->output_string = ipad_ostr.c_str(); omode->interconnect[0] = *o_ic; imode->interconnect[0] = *i_ic; @@ -1611,8 +1609,8 @@ struct ArchReader { ic->type = DIRECT_INTERC; ic->parent_mode_index = idx; ic->parent_mode = mode; - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; } create_ports(leaf, pins, name); @@ -1667,8 +1665,8 @@ struct ArchReader { ic->type = ic_type; ic->parent_mode_index = idx; ic->parent_mode = mode; - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; } /** @brief Processes all the ports of a given complex block. @@ -1787,8 +1785,8 @@ struct ArchReader { VTR_ASSERT(names.insert(ic_name).second); ic->name = vtr::strdup(ic_name.c_str()); - ic->input_string = vtr::strdup(input.c_str()); - ic->output_string = vtr::strdup(outputs_str.c_str()); + ic->input_string = input; + ic->output_string = outputs_str; } // Checks and, in case, adds all the necessary pack patterns to the marked interconnects @@ -2144,8 +2142,8 @@ struct ArchReader { ic->type = DIRECT_INTERC; ic->parent_mode_index = 0; ic->parent_mode = mode; - ic->input_string = vtr::strdup(istr.c_str()); - ic->output_string = vtr::strdup(ostr.c_str()); + ic->input_string = istr; + ic->output_string = ostr; count++; } diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index c73b35606e..2dc49f91b9 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -1850,10 +1850,10 @@ static void process_interconnect(vtr::string_internment& strings, mode->interconnect[interconnect_idx].parent_mode = mode; const char* prop = get_attribute(cur, "input", loc_data).value(); - mode->interconnect[interconnect_idx].input_string = vtr::strdup(prop); + mode->interconnect[interconnect_idx].input_string = prop; prop = get_attribute(cur, "output", loc_data).value(); - mode->interconnect[interconnect_idx].output_string = vtr::strdup(prop); + mode->interconnect[interconnect_idx].output_string = prop; prop = get_attribute(cur, "name", loc_data).value(); mode->interconnect[interconnect_idx].name = vtr::strdup(prop); diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 85f9730585..4e4bd5c0db 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -823,7 +823,7 @@ static void alloc_and_load_mode_interconnect(t_pb_graph_node* pb_graph_parent_no int *num_input_pb_graph_node_pins, *num_output_pb_graph_node_pins; /* number of pins in a set [0..num_sets-1] */ int num_input_pb_graph_node_sets, num_output_pb_graph_node_sets; /* Points to pins specified in the port string, later used to insert edges */ - t_pb_graph_pin ***input_pb_graph_node_pins, ***output_pb_graph_node_pins; /* [0..num_sets_in_port - 1][0..num_ptrs - 1] */ + /* [0..num_sets_in_port - 1][0..num_ptrs - 1] */ if (load_power_structures) { VTR_ASSERT(pb_graph_parent_node->interconnect_pins[mode->index] == nullptr); @@ -836,15 +836,15 @@ static void alloc_and_load_mode_interconnect(t_pb_graph_node* pb_graph_parent_no for (i = 0; i < mode->num_interconnect; i++) { /* determine the interconnect input and output pins */ - input_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string(mode->interconnect[i].line_num, pb_graph_parent_node, - pb_graph_children_nodes, mode->interconnect[i].input_string, - &num_input_pb_graph_node_pins, &num_input_pb_graph_node_sets, - true, true); - - output_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string(mode->interconnect[i].line_num, pb_graph_parent_node, - pb_graph_children_nodes, mode->interconnect[i].output_string, - &num_output_pb_graph_node_pins, &num_output_pb_graph_node_sets, - false, true); + t_pb_graph_pin*** input_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string(mode->interconnect[i].line_num, pb_graph_parent_node, + pb_graph_children_nodes, mode->interconnect[i].input_string, + &num_input_pb_graph_node_pins, &num_input_pb_graph_node_sets, + true, true); + + t_pb_graph_pin*** output_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string(mode->interconnect[i].line_num, pb_graph_parent_node, + pb_graph_children_nodes, mode->interconnect[i].output_string, + &num_output_pb_graph_node_pins, &num_output_pb_graph_node_sets, + false, true); if (load_power_structures) { alloc_and_load_interconnect_pins(&pb_graph_parent_node->interconnect_pins[mode->index][i], From d744f8cf0d05118c9627b89eb551a454f8c8b2df Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 17:04:20 -0400 Subject: [PATCH 08/14] call c_str() on deafult name string --- libs/libarchfpga/src/arch_util.cpp | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 2cb345ad52..621dc48e21 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -566,8 +566,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].num_pb_type_children = 1; lut_pb_type->modes[1].mode_power = new t_mode_power(); lut_pb_type->modes[1].pb_type_children = new t_pb_type[1]; - alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name, - lut_pb_type->modes[1].pb_type_children); + alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name, lut_pb_type->modes[1].pb_type_children); lut_pb_type->annotations.clear(); lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1; lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1]; @@ -597,7 +596,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->name); lut_pb_type->modes[1].interconnect[1].type = DIRECT_INTERC; - lut_pb_type->modes[1].interconnect[1].input_string = vtr::string_fmt("%s.%s", default_name, out_port->name); + lut_pb_type->modes[1].interconnect[1].input_string = vtr::string_fmt("%s.%s", default_name.c_str(), out_port->name); lut_pb_type->modes[1].interconnect[1].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name); lut_pb_type->modes[1].interconnect[1].infer_annotations = true; @@ -642,8 +641,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->modes[0].num_pb_type_children = 1; mem_pb_type->modes[0].pb_type_children = new t_pb_type[1]; - alloc_and_load_default_child_for_pb_type(mem_pb_type, default_name, - &mem_pb_type->modes[0].pb_type_children[0]); + alloc_and_load_default_child_for_pb_type(mem_pb_type, default_name, &mem_pb_type->modes[0].pb_type_children[0]); mem_pb_type->modes[0].pb_type_children[0].depth = mem_pb_type->depth + 1; mem_pb_type->modes[0].pb_type_children[0].parent_mode = &mem_pb_type->modes[0]; mem_pb_type->modes[0].pb_type_children[0].num_pb = num_pb; From 4ce0c34bb76068249dc2aedef836e4357fa6842b Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 17:13:52 -0400 Subject: [PATCH 09/14] local loop variables in arch_util.cpp --- libs/libarchfpga/src/arch_util.cpp | 66 +++++++++++++----------------- vpr/src/base/load_flat_place.cpp | 2 +- 2 files changed, 30 insertions(+), 38 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 621dc48e21..6a0afef655 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -2,6 +2,7 @@ #include #include #include +#include #include "logic_types.h" #include "physical_types.h" @@ -213,29 +214,27 @@ static void free_all_pb_graph_nodes(std::vector& type_desc } static void free_pb_graph(t_pb_graph_node* pb_graph_node) { - int i, j, k; - const t_pb_type* pb_type; - - pb_type = pb_graph_node->pb_type; + const t_pb_type* pb_type = pb_graph_node->pb_type; /*free all lists of connectable input pin pointer of pb_graph_node and it's children*/ /*free_list_of_connectable_input_pin_ptrs (pb_graph_node);*/ /* Free ports for pb graph node */ - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + for (int i = 0; i < pb_graph_node->num_input_ports; i++) { + for (int j = 0; j < pb_graph_node->num_input_pins[i]; j++) { if (pb_graph_node->input_pins[i][j].parent_pin_class) delete[] pb_graph_node->input_pins[i][j].parent_pin_class; } delete[] pb_graph_node->input_pins[i]; } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + + for (int i = 0; i < pb_graph_node->num_output_ports; i++) { + for (int j = 0; j < pb_graph_node->num_output_pins[i]; j++) { if (pb_graph_node->output_pins[i][j].parent_pin_class) delete[] pb_graph_node->output_pins[i][j].parent_pin_class; if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) { - for (k = 0; k < pb_graph_node->pb_type->depth; k++) { + for (int k = 0; k < pb_graph_node->pb_type->depth; k++) { delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]; } delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs; @@ -246,8 +245,9 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) { } delete[] pb_graph_node->output_pins[i]; } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + + for (int i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (int j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { if (pb_graph_node->clock_pins[i][j].parent_pin_class) delete[] pb_graph_node->clock_pins[i][j].parent_pin_class; } @@ -266,12 +266,12 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) { delete[] pb_graph_node->output_pin_class_size; if (pb_graph_node->interconnect_pins) { - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (int i = 0; i < pb_graph_node->pb_type->num_modes; i++) { if (pb_graph_node->interconnect_pins[i] == nullptr) continue; t_mode* mode = &pb_graph_node->pb_type->modes[i]; - for (j = 0; j < mode->num_interconnect; ++j) { + for (int j = 0; j < mode->num_interconnect; ++j) { //The interconnect_pins data structures are only initialized for power analysis and //are bizarrely baroque... t_interconnect* interconn = pb_graph_node->interconnect_pins[i][j].interconnect; @@ -293,9 +293,9 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) { delete[] pb_graph_node->interconnect_pins; delete pb_graph_node->pb_node_power; - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (int k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { free_pb_graph(&pb_graph_node->child_pb_graph_nodes[i][j][k]); } vtr::free(pb_graph_node->child_pb_graph_nodes[i][j]); @@ -339,17 +339,14 @@ static void free_pb_type(t_pb_type* pb_type) { } t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) { - t_port* port; int i; unsigned int high; unsigned int low; - unsigned int bracket_pos; - unsigned int colon_pos; - bracket_pos = strcspn(name, "["); + unsigned int bracket_pos = strcspn(name, "["); /* Find port by name */ - port = nullptr; + t_port* port = nullptr; for (i = 0; i < pb_type->num_ports; i++) { char* compare_to = pb_type->ports[i].name; @@ -367,7 +364,7 @@ t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, in if (strlen(name) > bracket_pos) { high = atoi(&name[bracket_pos + 1]); - colon_pos = strcspn(name, ":"); + unsigned int colon_pos = strcspn(name, ":"); if (colon_pos < strlen(name)) { low = atoi(&name[colon_pos + 1]); @@ -535,8 +532,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].num_interconnect = 1; lut_pb_type->modes[0].interconnect = new t_interconnect[1]; lut_pb_type->modes[0].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char)); - sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s", - lut_pb_type->name); + sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s", lut_pb_type->name); lut_pb_type->modes[0].interconnect[0].type = COMPLETE_INTERC; lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name); lut_pb_type->modes[0].interconnect[0].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name); @@ -580,8 +576,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].num_interconnect = 2; lut_pb_type->modes[1].interconnect = new t_interconnect[lut_pb_type->modes[1].num_interconnect]; lut_pb_type->modes[1].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char)); - sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s", - lut_pb_type->name); + sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s", lut_pb_type->name); lut_pb_type->modes[1].interconnect[0].type = DIRECT_INTERC; lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt(lut_pb_type->name, in_port->name); lut_pb_type->modes[1].interconnect[0].output_string = default_name + '.' + in_port->name; @@ -592,8 +587,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power(); lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char)); - sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s", - lut_pb_type->name); + sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s", lut_pb_type->name); lut_pb_type->modes[1].interconnect[1].type = DIRECT_INTERC; lut_pb_type->modes[1].interconnect[1].input_string = vtr::string_fmt("%s.%s", default_name.c_str(), out_port->name); @@ -867,7 +861,6 @@ void SyncModelsPbTypes_rec(t_arch* arch, */ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, t_pb_type* parent_pb_type) { - int i_port; bool clock_valid = false; //Determine if annotation's clock is same as primitive's clock if (!parent_pb_type || !annotation) { @@ -875,7 +868,7 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, "Annotation_clock check encounters invalid annotation or primitive.\n"); } - for (i_port = 0; i_port < parent_pb_type->num_ports; i_port++) { + for (int i_port = 0; i_port < parent_pb_type->num_ports; i_port++) { if (parent_pb_type->ports[i_port].is_clock) { if (parent_pb_type->ports[i_port].name == annotation->clock) { clock_valid = true; @@ -979,7 +972,7 @@ bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* po for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) { InstPort annot_in(annotation.input_pins); if (annot_in.port_name() == port->name) { - for (const auto& [key, _] : annotation.annotation_entries) { + for (const int key : annotation.annotation_entries | std::views::keys) { if (key == annot_type) { return true; } @@ -997,9 +990,8 @@ bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_ for (const std::string& annot_out_str : vtr::StringToken(annotation.output_pins).split(" \t\n")) { InstPort out_pins(annot_out_str); if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) { - for (const auto& [key, _] : annotation.annotation_entries) { - if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { + for (const int key : annotation.annotation_entries | std::views::keys) { + if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { return true; } } @@ -1031,7 +1023,7 @@ void link_physical_logical_types(std::vector& PhysicalTile return lhs_diff_num_pins < rhs_diff_num_pins; }; - std::sort(equivalent_sites.begin(), equivalent_sites.end(), criteria); + std::ranges::stable_sort(equivalent_sites, criteria); for (t_logical_block_type& logical_block : LogicalBlockTypes) { for (t_logical_block_type_ptr site : equivalent_sites) { @@ -1068,7 +1060,7 @@ void link_physical_logical_types(std::vector& PhysicalTile return lhs_diff_num_pins < rhs_diff_num_pins; }; - std::sort(equivalent_tiles.begin(), equivalent_tiles.end(), criteria); + std::ranges::stable_sort(equivalent_tiles, criteria); for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) { for (auto& tile : equivalent_tiles) { @@ -1076,7 +1068,7 @@ void link_physical_logical_types(std::vector& PhysicalTile for (auto& sub_tile : tile->sub_tiles) { auto equiv_sites = sub_tile.equivalent_sites; - if (std::find(equiv_sites.begin(), equiv_sites.end(), &logical_block) == equiv_sites.end()) { + if (std::ranges::find(equiv_sites, &logical_block) == equiv_sites.end()) { continue; } diff --git a/vpr/src/base/load_flat_place.cpp b/vpr/src/base/load_flat_place.cpp index 12ac4c7b6f..9c22b183e6 100644 --- a/vpr/src/base/load_flat_place.cpp +++ b/vpr/src/base/load_flat_place.cpp @@ -190,7 +190,7 @@ FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_pa bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { VTR_LOG("load_flat_placement(); when implemented, this function:"); VTR_LOG("\n\tLoads flat placement file: %s, ", vpr_setup.FileNameOpts.FlatPlaceFile.c_str()); - VTR_LOG("\n\tArch id: %s, ", arch.architecture_id); + VTR_LOG("\n\tArch id: %s, ", arch.architecture_id.c_str()); VTR_LOG("\n\tPrints clustered netlist file: %s, ", vpr_setup.FileNameOpts.NetFile.c_str()); VTR_LOG("\n\tPrints fix clusters file: %s\n", vpr_setup.FileNameOpts.write_constraints_file.c_str()); From c4eef9446b24d500a86cbd17515b2cb158bdd49a Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 17:27:32 -0400 Subject: [PATCH 10/14] add noexcept to criteria --- libs/libarchfpga/src/arch_util.cpp | 10 ++++----- libs/libarchfpga/src/read_xml_arch_file.cpp | 24 ++++++++++----------- vpr/src/base/load_flat_place.cpp | 2 +- vpr/src/base/load_flat_place.h | 2 +- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 6a0afef655..85312d6daf 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -140,14 +140,14 @@ InstPort::name_index InstPort::parse_name_index(const std::string& str) { int InstPort::num_instances() const { if (instance_high_index() == UNSPECIFIED || instance_low_index() == UNSPECIFIED) { - throw ArchFpgaError("Unspecified instance indicies"); + throw ArchFpgaError("Unspecified instance indices"); } return instance_high_index() - instance_low_index() + 1; } int InstPort::num_pins() const { if (port_high_index() == UNSPECIFIED || port_low_index() == UNSPECIFIED) { - throw ArchFpgaError("Unspecified port indicies"); + throw ArchFpgaError("Unspecified port indices"); } return port_high_index() - port_low_index() + 1; } @@ -1011,7 +1011,7 @@ void link_physical_logical_types(std::vector& PhysicalTile auto eq_sites_set = get_equivalent_sites_set(&physical_tile); auto equivalent_sites = std::vector(eq_sites_set.begin(), eq_sites_set.end()); - auto criteria = [&physical_tile](const t_logical_block_type* lhs, const t_logical_block_type* rhs) { + auto criteria = [&physical_tile](const t_logical_block_type* lhs, const t_logical_block_type* rhs) noexcept { int num_pins = physical_tile.num_inst_pins; int lhs_num_logical_pins = lhs->pb_type->num_pins; @@ -1048,7 +1048,7 @@ void link_physical_logical_types(std::vector& PhysicalTile std::unordered_map ignored_pins_check_map; std::unordered_map global_pins_check_map; - auto criteria = [&logical_block](const t_physical_tile_type* lhs, const t_physical_tile_type* rhs) { + auto criteria = [&logical_block](const t_physical_tile_type* lhs, const t_physical_tile_type* rhs) noexcept { int num_logical_pins = logical_block.pb_type->num_pins; int lhs_num_pins = lhs->num_inst_pins; @@ -1063,7 +1063,7 @@ void link_physical_logical_types(std::vector& PhysicalTile std::ranges::stable_sort(equivalent_tiles, criteria); for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) { - for (auto& tile : equivalent_tiles) { + for (t_physical_tile_type_ptr tile : equivalent_tiles) { auto direct_maps = tile->tile_block_pin_directs_map.at(logical_block.index); for (auto& sub_tile : tile->sub_tiles) { diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 2dc49f91b9..8a944ad9db 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2632,12 +2632,12 @@ static void process_block_type_locs(t_grid_def& grid_def, const pugiutil::loc_data& loc_data) { //Process all the block location specifications for (pugi::xml_node loc_spec_tag : layout_block_type_tag.children()) { - const char* loc_type = loc_spec_tag.name(); + std::string_view loc_type = loc_spec_tag.name(); // There are multiple attributes that are shared by every other tag that interposer // tags do not have. For this reason we check if loc_spec_tag is an interposer tag // and switch code paths if it is. - if (loc_type == std::string("interposer_cut")) { + if (loc_type == "interposer_cut") { if (grid_def.grid_type == e_grid_def_type::AUTO) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(loc_spec_tag), "Interposers are not currently supported for auto sized devices."); } @@ -2658,7 +2658,7 @@ static void process_block_type_locs(t_grid_def& grid_def, int priority = get_attribute(loc_spec_tag, "priority", loc_data).as_int(); t_metadata_dict meta = process_meta_data(strings, loc_spec_tag, loc_data); - if (loc_type == std::string("perimeter")) { + if (loc_type == "perimeter") { expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); //The edges @@ -2697,7 +2697,7 @@ static void process_block_type_locs(t_grid_def& grid_def, grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_edge)); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_edge)); - } else if (loc_type == std::string("corners")) { + } else if (loc_type == "corners") { expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); //The corners @@ -2736,7 +2736,7 @@ static void process_block_type_locs(t_grid_def& grid_def, grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_right)); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_right)); - } else if (loc_type == std::string("fill")) { + } else if (loc_type == "fill") { expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); t_grid_loc_def fill(type_name, priority); @@ -2750,7 +2750,7 @@ static void process_block_type_locs(t_grid_def& grid_def, grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(fill)); - } else if (loc_type == std::string("single")) { + } else if (loc_type == "single") { expect_only_attributes(loc_spec_tag, {"type", "priority", "x", "y"}, loc_data); t_grid_loc_def single(type_name, priority); @@ -2764,7 +2764,7 @@ static void process_block_type_locs(t_grid_def& grid_def, grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(single)); - } else if (loc_type == std::string("col")) { + } else if (loc_type == "col") { expect_only_attributes(loc_spec_tag, {"type", "priority", "startx", "repeatx", "starty", "incry"}, loc_data); t_grid_loc_def col(type_name, priority); @@ -2794,7 +2794,7 @@ static void process_block_type_locs(t_grid_def& grid_def, grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(col)); - } else if (loc_type == std::string("row")) { + } else if (loc_type == "row") { expect_only_attributes(loc_spec_tag, {"type", "priority", "starty", "repeaty", "startx", "incrx"}, loc_data); t_grid_loc_def row(type_name, priority); @@ -2823,7 +2823,7 @@ static void process_block_type_locs(t_grid_def& grid_def, row.meta = row.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(row)); - } else if (loc_type == std::string("region")) { + } else if (loc_type == "region") { expect_only_attributes(loc_spec_tag, {"type", "priority", "startx", "endx", "repeatx", "incrx", @@ -4094,12 +4094,12 @@ static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int std::vector& part_len = segment.part_len; bool& is_bend = segment.is_bend; - std::string tmp = std::string(get_attribute(node, "type", loc_data).value()); + std::string tmp = get_attribute(node, "type", loc_data).value(); if (tmp == "pattern") { int i = 0; - /* Get the content string */ - std::string content = std::string(node.child_value()); + // Get the content string + std::string content = node.child_value(); for (char c : content) { switch (c) { case ' ': diff --git a/vpr/src/base/load_flat_place.cpp b/vpr/src/base/load_flat_place.cpp index 9c22b183e6..c41552a405 100644 --- a/vpr/src/base/load_flat_place.cpp +++ b/vpr/src/base/load_flat_place.cpp @@ -187,7 +187,7 @@ FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_pa } /* ingests and legalizes a flat placement file */ -bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { +bool load_flat_placement(const t_vpr_setup& vpr_setup, const t_arch& arch) { VTR_LOG("load_flat_placement(); when implemented, this function:"); VTR_LOG("\n\tLoads flat placement file: %s, ", vpr_setup.FileNameOpts.FlatPlaceFile.c_str()); VTR_LOG("\n\tArch id: %s, ", arch.architecture_id.c_str()); diff --git a/vpr/src/base/load_flat_place.h b/vpr/src/base/load_flat_place.h index 7776d7f658..62ccefc015 100644 --- a/vpr/src/base/load_flat_place.h +++ b/vpr/src/base/load_flat_place.h @@ -59,7 +59,7 @@ FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_pa /** * @brief A function that loads and legalizes a flat placement file */ -bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch); +bool load_flat_placement(const t_vpr_setup& vpr_setup, const t_arch& arch); /** * @brief Logs information on the quality of the clustering and placement From 3b938f680ca87be46224171454dee01bb0130909 Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 17:40:14 -0400 Subject: [PATCH 11/14] get rid of redundant calls to std::string constructor --- libs/libarchfpga/src/read_xml_arch_file.cpp | 17 ++++++++--------- vpr/src/base/read_netlist.cpp | 2 +- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 8a944ad9db..99440a62d7 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -779,7 +779,7 @@ static std::pair process_instance_string(pugi::xml_node Locations, size_t token_index = 0; t_token token = tokens[token_index]; - if (token.type != e_token_type::STRING || std::string(token.data) != sub_tile.name) { + if (token.type != e_token_type::STRING || token.data != sub_tile.name) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), vtr::string_fmt("Wrong physical type name of the port: %s\n", pin_loc_string).c_str()); } @@ -2114,7 +2114,7 @@ static void process_fc(pugi::xml_node node, static t_fc_override process_fc_override(pugi::xml_node node, const pugiutil::loc_data& loc_data) { if (node.name() != std::string("fc_override")) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), - vtr::string_fmt("Unexpeted node of type '%s' (expected optional 'fc_override')", + vtr::string_fmt("Unexpected node of type '%s' (expected optional 'fc_override')", node.name()) .c_str()); } @@ -3366,12 +3366,11 @@ static void process_equivalent_site_custom_connection(pugi::xml_node Parent, expect_only_attributes(cur_direct, {"from", "to"}, loc_data); - std::string from, to; // `from` attribute is relative to the physical tile pins - from = std::string(get_attribute(cur_direct, "from", loc_data).value()); + const std::string from = get_attribute(cur_direct, "from", loc_data).value(); // `to` attribute is relative to the logical block pins - to = std::string(get_attribute(cur_direct, "to", loc_data).value()); + const std::string to = get_attribute(cur_direct, "to", loc_data).value(); auto from_pins = process_pin_string(cur_direct, sub_tile, from.c_str(), loc_data); auto to_pins = process_pin_string(cur_direct, logical_block_type, to.c_str(), loc_data); @@ -3820,7 +3819,7 @@ static std::vector process_segments(pugi::xml_node parent, /* Get segment name */ tmp = get_attribute(node, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { - segs[i].name = std::string(tmp); + segs[i].name = tmp; } else { /* if swich block is "custom", then you have to provide a name for segment */ if (switchblocklist_required) { @@ -3832,7 +3831,7 @@ static std::vector process_segments(pugi::xml_node parent, ss << "unnamed_segment_" << i; std::string dummy = ss.str(); tmp = dummy.c_str(); - segs[i].name = std::string(tmp); + segs[i].name = tmp; } /* Get segment length */ @@ -4396,14 +4395,14 @@ static std::vector process_switches(pugi::xml_node Parent, // Check for switch name collisions for (int j = 0; j < i; ++j) { - if (0 == strcmp(switches[j].name.c_str(), switch_name)) { + if (switches[j].name == switch_name) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(node), vtr::string_fmt("Two switches with the same name '%s' were found.\n", switch_name) .c_str()); } } - arch_switch.name = std::string(switch_name); + arch_switch.name = switch_name; /* Figure out the type of switch */ /* As noted above, due to their configuration of pass transistors feeding into a buffer, diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index cbc943debe..7b5bed8a4a 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -134,7 +134,7 @@ ClusteredNetlist read_netlist(const char* net_file, auto msg = vtr::string_fmt( "Netlist was generated from a different architecture file" " (loaded architecture ID: %s, netlist file architecture ID: %s)", - arch->architecture_id, arch_id.c_str()); + arch->architecture_id.c_str(), arch_id.c_str()); if (verify_file_digests) { vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(top), msg.c_str()); } else { From 94864ae61f2ee58f83371151c57e37679d70c9ce Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 18:04:13 -0400 Subject: [PATCH 12/14] call c_str() --- vpr/src/pack/pb_type_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 4e4bd5c0db..bb559234bd 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -886,8 +886,8 @@ static void alloc_and_load_mode_interconnect(t_pb_graph_node* pb_graph_parent_no vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), mode->interconnect[i].line_num, "Unknown interconnect %d for mode %s in pb_type %s, input %s, output %s\n", mode->interconnect[i].type, mode->name, - pb_graph_parent_node->pb_type->name, mode->interconnect[i].input_string, - mode->interconnect[i].output_string); + pb_graph_parent_node->pb_type->name, mode->interconnect[i].input_string.c_str(), + mode->interconnect[i].output_string.c_str()); } for (j = 0; j < num_input_pb_graph_node_sets; j++) { delete[] input_pb_graph_node_pins[j]; From 84dbbe28e1090f76988deb377f6e7287b47d7160 Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Wed, 29 Oct 2025 18:22:30 -0400 Subject: [PATCH 13/14] fix forward declaration --- vpr/src/analytical_place/ap_draw_manager.h | 2 +- .../route/router_lookahead/router_lookahead_compressed_map.h | 2 +- vpr/src/timing/PreClusterTimingManager.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/analytical_place/ap_draw_manager.h b/vpr/src/analytical_place/ap_draw_manager.h index 0015d61581..aed89d77df 100644 --- a/vpr/src/analytical_place/ap_draw_manager.h +++ b/vpr/src/analytical_place/ap_draw_manager.h @@ -10,7 +10,7 @@ #include // Forward declarations -class PartialPlacement; +struct PartialPlacement; // Types to indicate the type of drawing operation enum class APDrawType { diff --git a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h index 59bd3d061d..558492e82d 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h +++ b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h @@ -37,7 +37,7 @@ class CompressedMapLookahead : public RouterLookahead { VPR_THROW(VPR_ERROR_ROUTE, "CompressedMapLookahead::read unimplemented"); } - void read_intra_cluster(const std::string& /*file*/) { + void read_intra_cluster(const std::string& /*file*/) override { VPR_THROW(VPR_ERROR_ROUTE, "CompressedMapLookahead::read_intra_cluster unimplemented"); } diff --git a/vpr/src/timing/PreClusterTimingManager.h b/vpr/src/timing/PreClusterTimingManager.h index 1560b301c4..ae8c5d171f 100644 --- a/vpr/src/timing/PreClusterTimingManager.h +++ b/vpr/src/timing/PreClusterTimingManager.h @@ -15,7 +15,7 @@ // Forward declarations. class AtomLookup; class AtomNetlist; -class PartialPlacement; +struct PartialPlacement; class PlaceDelayModel; class PreClusterDelayCalculator; class Prepacker; From 8aa70b5a5f274b543db0484e2ab57af1d3dbe15f Mon Sep 17 00:00:00 2001 From: Soheil Shahrouz Date: Thu, 30 Oct 2025 14:04:14 -0400 Subject: [PATCH 14/14] fixed segfault --- libs/libarchfpga/src/arch_util.cpp | 23 ++++++++++----------- libs/libarchfpga/src/read_xml_arch_file.cpp | 13 ++++++------ libs/libarchfpga/src/read_xml_arch_file.h | 8 +++++-- libs/libvtrutil/src/vtr_digest.cpp | 6 +++--- libs/libvtrutil/src/vtr_digest.h | 2 +- libs/libvtrutil/src/vtr_util.cpp | 2 +- vpr/src/pack/pb_type_graph.cpp | 14 ++++++------- vpr/src/pack/pb_type_graph_annotations.cpp | 2 +- 8 files changed, 36 insertions(+), 34 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 85312d6daf..1dd153b7fd 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -51,8 +51,7 @@ InstPort::InstPort(const std::string& str) { instance_ = parse_name_index(inst_port[0]); port_ = parse_name_index(inst_port[1]); } else { - std::string msg = vtr::string_fmt("Failed to parse instance port specification '%s'", - str.c_str()); + std::string msg = vtr::string_fmt("Failed to parse instance port specification '%s'", str.c_str()); throw ArchFpgaError(msg); } } @@ -534,7 +533,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char)); sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s", lut_pb_type->name); lut_pb_type->modes[0].interconnect[0].type = COMPLETE_INTERC; - lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name); + lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name); lut_pb_type->modes[0].interconnect[0].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name); lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0; @@ -578,7 +577,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char)); sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s", lut_pb_type->name); lut_pb_type->modes[1].interconnect[0].type = DIRECT_INTERC; - lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt(lut_pb_type->name, in_port->name); + lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name); lut_pb_type->modes[1].interconnect[0].output_string = default_name + '.' + in_port->name; lut_pb_type->modes[1].interconnect[0].infer_annotations = true; @@ -686,14 +685,14 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1; mem_pb_type->modes[0].pb_type_children[0].num_input_pins -= (mem_pb_type->ports[i].num_pins - 1); - mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:0].%s", output_name, num_pb - 1, output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name.data(), input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:0].%s", output_name.data(), num_pb - 1, output_port_name); } else { /* force data pins to be one bit wide and update stats */ mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1; mem_pb_type->modes[0].pb_type_children[0].num_output_pins -= (mem_pb_type->ports[i].num_pins - 1); - mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:0].%s", input_name, num_pb - 1, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:0].%s", input_name.data(), num_pb - 1, input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name.data(), output_port_name); } /* Allocate interconnect power structures */ @@ -710,12 +709,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { if (mem_pb_type->ports[i].type == IN_PORT) { mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC; - mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:%d].%s", output_name, j, j, output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name.data(), input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:%d].%s", output_name.data(), j, j, output_port_name); } else { mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC; - mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:%d].%s", input_name, j, j, input_port_name); - mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name); + mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:%d].%s", input_name.data(), j, j, input_port_name); + mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name.data(), output_port_name); } /* Allocate interconnect power structures */ diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 99440a62d7..85b515aa86 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -395,8 +395,7 @@ static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int * */ -/* Loads the given architecture file. */ -void xml_read_arch(const char* arch_file, +void xml_read_arch(std::string_view arch_file, const bool timing_enabled, t_arch* arch, std::vector& physical_tile_types, @@ -408,7 +407,7 @@ void xml_read_arch(const char* arch_file, arch_file); } - //Create a unique identifier for this architecture file based on it's contents + // Create a unique identifier for this architecture file based on it's contents arch->architecture_id = vtr::secure_digest_file(arch_file); // Parse the file @@ -418,11 +417,11 @@ void xml_read_arch(const char* arch_file, t_default_fc_spec arch_def_fc; pugi::xml_document doc; pugi::xml_node next; - pugiutil::loc_data loc_data = pugiutil::load_xml(doc, arch_file); + pugiutil::loc_data loc_data = pugiutil::load_xml(doc, arch_file.data()); - set_arch_file_name(arch_file); + set_arch_file_name(arch_file.data()); - /* Root node should be architecture */ + // Root node should be architecture auto architecture = get_single_child(doc, "architecture", loc_data); /* TODO: do version processing properly with string delimiting on the . */ @@ -565,7 +564,7 @@ void xml_read_arch(const char* arch_file, mark_IO_types(physical_tile_types); } catch (pugiutil::XmlError& e) { - archfpga_throw(arch_file, e.line(), e.what()); + archfpga_throw(arch_file.data(), e.line(), e.what()); } } diff --git a/libs/libarchfpga/src/read_xml_arch_file.h b/libs/libarchfpga/src/read_xml_arch_file.h index b092fb6138..610bcf812c 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.h +++ b/libs/libarchfpga/src/read_xml_arch_file.h @@ -1,6 +1,8 @@ #pragma once #include +#include + #include "physical_types.h" #ifdef __cplusplus @@ -11,8 +13,10 @@ extern "C" { * should use the pointers to these type indices*/ #define EMPTY_TYPE_INDEX 0 -/* function declarations */ -void xml_read_arch(const char* arch_file, +// function declarations + +/// Loads the given architecture file +void xml_read_arch(std::string_view arch_file, const bool timing_enabled, t_arch* arch, std::vector& physical_tile_types, diff --git a/libs/libvtrutil/src/vtr_digest.cpp b/libs/libvtrutil/src/vtr_digest.cpp index d5d90f12c4..9367e923ea 100644 --- a/libs/libvtrutil/src/vtr_digest.cpp +++ b/libs/libvtrutil/src/vtr_digest.cpp @@ -14,10 +14,10 @@ namespace vtr { -std::string secure_digest_file(const std::string& filepath) { - std::ifstream is(filepath); +std::string secure_digest_file(std::string_view filepath) { + std::ifstream is(filepath.data()); if (!is) { - throw VtrError("Failed to open file", filepath); + throw VtrError("Failed to open file", filepath.data()); } return secure_digest_stream(is); } diff --git a/libs/libvtrutil/src/vtr_digest.h b/libs/libvtrutil/src/vtr_digest.h index 75130bcb99..40c05b3019 100644 --- a/libs/libvtrutil/src/vtr_digest.h +++ b/libs/libvtrutil/src/vtr_digest.h @@ -6,7 +6,7 @@ namespace vtr { ///@brief Generate a secure hash of the file at filepath -std::string secure_digest_file(const std::string& filepath); +std::string secure_digest_file(std::string_view filepath); ///@brief Generate a secure hash of a stream std::string secure_digest_stream(std::istream& is); diff --git a/libs/libvtrutil/src/vtr_util.cpp b/libs/libvtrutil/src/vtr_util.cpp index 180faeff64..5181798a05 100644 --- a/libs/libvtrutil/src/vtr_util.cpp +++ b/libs/libvtrutil/src/vtr_util.cpp @@ -65,7 +65,7 @@ std::string string_fmt(const char* fmt, ...) { // Initialize variable argument list va_start(va_args, fmt); - //Format string + // Format string std::string str = vstring_fmt(fmt, va_args); // Reset variable argument list diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index bb559234bd..030f4fca0c 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -967,13 +967,13 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num, if (tokens[i].type == e_token_type::OPEN_SQUIG_BRACKET) { if (in_squig_bracket) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, - "{ inside { in port %s\n", port_string); + "{ inside { in port %s\n", port_string.data()); } in_squig_bracket = true; } else if (tokens[i].type == e_token_type::CLOSE_SQUIG_BRACKET) { if (!in_squig_bracket) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, - "No matching '{' for '}' in port %s\n", port_string); + "No matching '{' for '}' in port %s\n", port_string.data()); } (*num_sets)++; in_squig_bracket = false; @@ -987,7 +987,7 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num, if (in_squig_bracket) { (*num_sets)++; vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, - "No matching '{' for '}' in port %s\n", port_string); + "No matching '{' for '}' in port %s\n", port_string.data()); } t_pb_graph_pin*** pb_graph_pins = new t_pb_graph_pin**[*num_sets]; @@ -1003,17 +1003,17 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num, if (tokens[i].type == e_token_type::OPEN_SQUIG_BRACKET) { if (in_squig_bracket) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, - "{ inside { in port %s\n", port_string); + "{ inside { in port %s\n", port_string.data()); } in_squig_bracket = true; } else if (tokens[i].type == e_token_type::CLOSE_SQUIG_BRACKET) { if ((*num_ptrs)[curr_set] == 0) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, - "No data contained in {} in port %s\n", port_string); + "No data contained in {} in port %s\n", port_string.data()); } if (!in_squig_bracket) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, - "No matching '{' for '}' in port %s\n", port_string); + "No matching '{' for '}' in port %s\n", port_string.data()); } curr_set++; in_squig_bracket = false; @@ -1026,7 +1026,7 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num, &((*num_ptrs)[curr_set]), &pb_graph_pins[curr_set]); } catch (VprError& e) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, - "Syntax error processing port string '%s' (%s)\n", port_string, e.what()); + "Syntax error processing port string '%s' (%s)\n", port_string.data(), e.what()); } VTR_ASSERT(success); diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index 3986792c71..4e33925779 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -568,7 +568,7 @@ static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, std::string_view c } } - if (clock_pin != nullptr) { + if (clock_pin == nullptr) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num, "Failed to find associated clock pin"); }