From 57837dba96e3aae6d6db591ea1bd4feecddfacde Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Mon, 17 Nov 2025 07:10:49 -0800 Subject: [PATCH 01/13] [libs][rr_graph] set T_linear for IPIN based on the most frequent switch connected to it --- .../utils/alloc_and_load_rr_indexed_data.cpp | 27 ++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 3e25213125..159d84fe5c 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -2,6 +2,7 @@ #include #include /* Needed only for sqrt call (remove if sqrt removed) */ +#include #include #include #include @@ -108,9 +109,6 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph, rr_indexed_data[RRIndexedDataId(i)].C_load = 0.; } - //TODO: SM: IPIN t_linear assumes wire_to_ipin_switch which corresponds to within die switch connection - rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = rr_graph.rr_switch_inf(wire_to_ipin_switch).Tdel; - std::vector ortho_costs = find_ortho_cost_index(rr_graph, segment_inf_x, segment_inf_y, e_parallel_axis::X_AXIS); /* AA: The code below should replace find_ortho_cost_index call once we deprecate the CLASSIC lookahead as it is the only lookahead @@ -531,12 +529,25 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector> switch_Cinternal_total(rr_indexed_data.size()); vtr::vector switches_buffered(rr_indexed_data.size(), LIBRRGRAPH_UNDEFINED_VAL); + std::map ipin_switch_count; + // Walk through the RR graph and collect all R and C values of all the nodes, // as well as their fan-in switches R, T_del, and Cinternal values. // The median of R and C values for each cost index is assigned to the indexed data. for (const RRNodeId rr_id : rr_graph.nodes()) { e_rr_type rr_type = rr_graph.node_type(rr_id); + if (rr_type == e_rr_type::IPIN) { + for (const RREdgeId edge : fan_in_list[rr_id]) { + short switch_index = rr_graph.rr_nodes().edge_switch(edge); + if (ipin_switch_count.find(switch_index) == ipin_switch_count.end()) { + ipin_switch_count[switch_index] = 1; + } else { + ipin_switch_count[switch_index]++; + } + } + } + if (!is_chanxy(rr_type) && !is_chanz(rr_type)) { continue; } @@ -590,6 +601,16 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, } } + int most_frequent_ipin_switch = -1; + for (const auto& [switch_index, count] : ipin_switch_count) { + if (count > most_frequent_ipin_switch_count) { + most_frequent_ipin_switch = switch_index; + } + } + VTR_ASSERT(most_frequent_ipin_switch != -1); + rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = rr_graph.rr_switch_inf(RRSwitchId(most_frequent_ipin_switch)).Tdel; + + unsigned num_occurences_of_no_instances_with_cost_index = 0; for (size_t cost_index = CHANX_COST_INDEX_START; cost_index < rr_indexed_data.size(); cost_index++) { if (num_nodes_of_index[RRIndexedDataId(cost_index)] == 0) { // Segments don't exist. From 129fd8804df72f5bb9c75c5103655a411937e637 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Mon, 17 Nov 2025 07:32:05 -0800 Subject: [PATCH 02/13] [libs][rr_graph] print a warning if IPIN switch block doesn't match the one specified in architecture file --- .../utils/alloc_and_load_rr_indexed_data.cpp | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 159d84fe5c..dfb6566adb 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -29,7 +29,9 @@ static void load_rr_indexed_data_base_costs(const RRGraphView& rr_graph, static float get_delay_normalization_fac(const vtr::vector& rr_indexed_data, const bool echo_enabled, const char* echo_file_name); -static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector& rr_indexed_data); +static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, + const RRSwitchId wire_to_ipin_switch, + vtr::vector& rr_indexed_data); /** * @brief Computes average R, Tdel, and Cinternal of fan-in switches for a given node. @@ -85,7 +87,7 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph, const std::vector& segment_inf_y, const std::vector& segment_inf_z, vtr::vector& rr_indexed_data, - RRSwitchId wire_to_ipin_switch, + const RRSwitchId wire_to_ipin_switch, e_base_cost_type base_cost_type, const bool echo_enabled, const char* echo_file_name) { @@ -156,7 +158,9 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph, rr_indexed_data[index].seg_index = seg_ptr->seg_index; } - load_rr_indexed_data_T_values(rr_graph, rr_indexed_data); + load_rr_indexed_data_T_values(rr_graph, + wire_to_ipin_switch, + rr_indexed_data); fixup_rr_indexed_data_T_values(rr_indexed_data, total_num_segment); @@ -511,6 +515,7 @@ static float get_delay_normalization_fac(const vtr::vector& rr_indexed_data) { vtr::vector> fan_in_list = get_fan_in_list(rr_graph); @@ -529,7 +534,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector> switch_Cinternal_total(rr_indexed_data.size()); vtr::vector switches_buffered(rr_indexed_data.size(), LIBRRGRAPH_UNDEFINED_VAL); - std::map ipin_switch_count; + std::map ipin_switch_count; // Walk through the RR graph and collect all R and C values of all the nodes, // as well as their fan-in switches R, T_del, and Cinternal values. @@ -601,15 +606,22 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, } } - int most_frequent_ipin_switch = -1; + short most_frequent_ipin_switch = -1; + size_t most_frequent_ipin_switch_count = 0; for (const auto& [switch_index, count] : ipin_switch_count) { if (count > most_frequent_ipin_switch_count) { most_frequent_ipin_switch = switch_index; + most_frequent_ipin_switch_count = count; } } VTR_ASSERT(most_frequent_ipin_switch != -1); rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = rr_graph.rr_switch_inf(RRSwitchId(most_frequent_ipin_switch)).Tdel; - + short wire_to_ipin_switch_index = static_cast(size_t(wire_to_ipin_switch)); + if (most_frequent_ipin_switch != wire_to_ipin_switch_index) { + VTR_LOG_WARN("Most frequent ipin switch %d is not the same as the wire_to_ipin_switch %d\n", + most_frequent_ipin_switch, + wire_to_ipin_switch_index); + } unsigned num_occurences_of_no_instances_with_cost_index = 0; for (size_t cost_index = CHANX_COST_INDEX_START; cost_index < rr_indexed_data.size(); cost_index++) { From 4dd6a634a626887cf194a717fcfae50e68373b1c Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Mon, 17 Nov 2025 08:04:34 -0800 Subject: [PATCH 03/13] [lib][rr_graph] add const identifier for const params passed to calculate_average_switch --- .../src/utils/alloc_and_load_rr_indexed_data.cpp | 14 +++++++++++--- .../src/utils/alloc_and_load_rr_indexed_data.h | 2 +- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index dfb6566adb..4efd7de055 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -52,7 +52,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int& num_switches, int& num_shorts, short& buffered, - vtr::vector>& fan_in_list); + const vtr::vector>& fan_in_list); static void fixup_rr_indexed_data_T_values(vtr::vector& rr_indexed_data, size_t num_segment); @@ -566,7 +566,15 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, int num_switches = 0; int num_shorts = 0; short buffered = LIBRRGRAPH_UNDEFINED_VAL; - calculate_average_switch(rr_graph, rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list); + calculate_average_switch(rr_graph, + rr_id, + avg_switch_R, + avg_switch_T, + avg_switch_Cinternal, + num_switches, + num_shorts, + buffered, + fan_in_list); if (num_switches == 0) { if (num_shorts == 0) { @@ -683,7 +691,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int& num_switches, int& num_shorts, short& buffered, - vtr::vector>& fan_in_list) { + const vtr::vector>& fan_in_list) { avg_switch_R = 0; avg_switch_T = 0; diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h index f98a4d4572..8d60ff93d1 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h @@ -12,7 +12,7 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph, const std::vector& segment_inf_y, const std::vector& segment_inf_z, vtr::vector& rr_indexed_data, - RRSwitchId wire_to_ipin_switch, + const RRSwitchId wire_to_ipin_switch, e_base_cost_type base_cost_type, const bool echo_enabled, const char* echo_file_name); From a94742ae2617a6112d47539ba6562343e80a47fe Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Wed, 19 Nov 2025 12:00:24 -0800 Subject: [PATCH 04/13] [lib][rr_graph][rr_indexed] use avg ipin for t_linear when building RR Graph --- .../utils/alloc_and_load_rr_indexed_data.cpp | 34 +++++++------------ 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 4efd7de055..59bbbba33e 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -534,7 +534,8 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector> switch_Cinternal_total(rr_indexed_data.size()); vtr::vector switches_buffered(rr_indexed_data.size(), LIBRRGRAPH_UNDEFINED_VAL); - std::map ipin_switch_count; + size_t ipin_switch_count = 0; + float ipin_switch_T_total = 0.; // Walk through the RR graph and collect all R and C values of all the nodes, // as well as their fan-in switches R, T_del, and Cinternal values. @@ -544,12 +545,9 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, if (rr_type == e_rr_type::IPIN) { for (const RREdgeId edge : fan_in_list[rr_id]) { - short switch_index = rr_graph.rr_nodes().edge_switch(edge); - if (ipin_switch_count.find(switch_index) == ipin_switch_count.end()) { - ipin_switch_count[switch_index] = 1; - } else { - ipin_switch_count[switch_index]++; - } + RRSwitchId rr_switch_id = RRSwitchId(rr_graph.edge_switch(edge)); + ipin_switch_T_total += rr_graph.rr_switch_inf(rr_switch_id).Tdel; + ipin_switch_count++; } } @@ -614,22 +612,16 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, } } - short most_frequent_ipin_switch = -1; - size_t most_frequent_ipin_switch_count = 0; - for (const auto& [switch_index, count] : ipin_switch_count) { - if (count > most_frequent_ipin_switch_count) { - most_frequent_ipin_switch = switch_index; - most_frequent_ipin_switch_count = count; + // Set the T_linear value for the IPIN cost index + { + if (ipin_switch_count == 0) { + VTR_LOG_WARN("No IPIN switches found. Setting T_linear to 0\n"); + float default_ipin_switch_T_del = rr_graph.rr_switch_inf(RRSwitchId(wire_to_ipin_switch)).Tdel; + rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = default_ipin_switch_T_del; + } else { + rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = ipin_switch_T_total / ipin_switch_count; } } - VTR_ASSERT(most_frequent_ipin_switch != -1); - rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = rr_graph.rr_switch_inf(RRSwitchId(most_frequent_ipin_switch)).Tdel; - short wire_to_ipin_switch_index = static_cast(size_t(wire_to_ipin_switch)); - if (most_frequent_ipin_switch != wire_to_ipin_switch_index) { - VTR_LOG_WARN("Most frequent ipin switch %d is not the same as the wire_to_ipin_switch %d\n", - most_frequent_ipin_switch, - wire_to_ipin_switch_index); - } unsigned num_occurences_of_no_instances_with_cost_index = 0; for (size_t cost_index = CHANX_COST_INDEX_START; cost_index < rr_indexed_data.size(); cost_index++) { From a0e4de999a7878d0a2f4873557011b2b04de9b9d Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Wed, 19 Nov 2025 12:36:38 -0800 Subject: [PATCH 05/13] fix a typo --- .../librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 59bbbba33e..9438577902 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -546,7 +546,8 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, if (rr_type == e_rr_type::IPIN) { for (const RREdgeId edge : fan_in_list[rr_id]) { RRSwitchId rr_switch_id = RRSwitchId(rr_graph.edge_switch(edge)); - ipin_switch_T_total += rr_graph.rr_switch_inf(rr_switch_id).Tdel; + float switch_T_del = rr_graph.rr_switch_inf(rr_switch_id).Tdel; + ipin_switch_T_total += switch_T_del; ipin_switch_count++; } } @@ -619,7 +620,8 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, float default_ipin_switch_T_del = rr_graph.rr_switch_inf(RRSwitchId(wire_to_ipin_switch)).Tdel; rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = default_ipin_switch_T_del; } else { - rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = ipin_switch_T_total / ipin_switch_count; + float average_ipin_switch_T_del = ipin_switch_T_total / ipin_switch_count; + rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = average_ipin_switch_T_del; } } From 9d025f2937fcd0e438936da4960486ee9a3051a2 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 20 Nov 2025 14:11:06 -0800 Subject: [PATCH 06/13] [ci] update vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt --- .../strong_global_nonuniform/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index 6cf16d404c..8f912c0b63 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -4,4 +4,4 @@ x_uniform_y_gaussian.xml stereovision3.v common 1.33 vpr 66.17 MiB 0.05 9984 -1 x_gaussian_y_gaussian.xml stereovision3.v common 1.26 vpr 66.74 MiB 0.04 9984 -1 -1 4 0.14 -1 -1 32896 -1 -1 13 11 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:28:24 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 68340 11 30 260 290 2 106 54 7 7 49 clb auto 26.8 MiB 0.07 601.862 415 7500 3474 3814 212 66.7 MiB 0.06 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.000420861 0.000372307 0.0357748 0.0315707 -1 -1 -1 -1 16 304 3 1.07788e+06 700622 -1 -1 0.14 0.0929463 0.080899 2680 3516 -1 306 2 153 243 10605 5221 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0111504 0.0106978 x_delta_y_uniform.xml stereovision3.v common 1.32 vpr 66.74 MiB 0.05 9984 -1 -1 4 0.14 -1 -1 32544 -1 -1 13 11 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:28:24 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 68344 11 30 260 290 2 106 54 7 7 49 clb auto 27.1 MiB 0.07 601.862 453 8622 3876 4500 246 66.7 MiB 0.06 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.000400646 0.000352807 0.037236 0.0328628 -1 -1 -1 -1 54 353 3 1.07788e+06 700622 -1 -1 0.15 0.113626 0.0980206 2680 3516 -1 353 2 154 244 12337 6086 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0111242 0.0106621 x_delta_y_delta.xml stereovision3.v common 1.30 vpr 66.18 MiB 0.05 9984 -1 -1 4 0.14 -1 -1 32744 -1 -1 13 11 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:28:24 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 67768 11 30 260 290 2 106 54 7 7 49 clb auto 26.8 MiB 0.07 601.862 503 8316 3040 5059 217 66.2 MiB 0.06 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.000406632 0.000359209 0.0365042 0.0322637 -1 -1 -1 -1 54 414 9 1.07788e+06 700622 -1 -1 0.14 0.0991422 0.085994 2680 3516 -1 405 3 166 259 13189 6834 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0118513 0.0112383 -x_uniform_y_delta.xml stereovision3.v common 1.38 vpr 66.75 MiB 0.05 9984 -1 -1 4 0.14 -1 -1 32736 -1 -1 13 11 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:28:24 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 68348 11 30 260 290 2 106 54 7 7 49 clb auto 26.8 MiB 0.07 601.862 446 8316 3491 4630 195 66.7 MiB 0.06 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.0004055 0.000356054 0.0368358 0.0325089 -1 -1 -1 -1 28 335 16 1.07788e+06 700622 -1 -1 0.24 0.152146 0.130266 2680 3516 -1 331 14 275 576 23209 9948 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0188403 0.0171122 +x_uniform_y_delta.xml stereovision3.v common 1.38 vpr 66.75 MiB 0.05 9984 -1 -1 4 0.14 -1 -1 32736 -1 -1 13 11 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:28:24 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 68348 11 30 260 290 2 106 54 7 7 49 clb auto 26.8 MiB 0.07 601.862 446 8316 3491 4630 195 66.7 MiB 0.06 0.00 1.90541 1.90541 -132.779 -1.90541 1.84522 0.00 0.0004055 0.000356054 0.0368358 0.0325089 -1 -1 -1 -1 30 335 16 1.07788e+06 700622 -1 -1 0.24 0.152146 0.130266 2680 3516 -1 331 14 275 576 23209 9948 1.90541 1.84522 -132.779 -1.90541 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0188403 0.0171122 From 439c236c559a58137253e2186e1e9979ac9d7133 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 20 Nov 2025 14:30:27 -0800 Subject: [PATCH 07/13] [ci] update goldne for stron_ap strong_bidir and strong_cock_aliases --- .../naive_full_legalizer/config/golden_results.txt | 2 +- .../vtr_reg_strong/strong_bidir/config/golden_results.txt | 2 +- .../strong_clock_aliases/config/golden_results.txt | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt index 3800ed0ac4..76b5b7ee71 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.64 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 135 9 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 77064 9 19 896 28 0 660 163 16 16 256 -1 mcnc_medium -1 -1 7727.83 7087 9508 603 6937 1968 75.3 MiB 2.09 0.00 6.3343 5.39115 -88.0884 -5.39115 nan 0.00 0.00133719 0.00116801 0.0488072 0.0445052 75.3 MiB 2.09 75.3 MiB 1.41 11108 16.8558 2920 4.43096 4709 24240 778883 128039 1.05632e+07 7.27569e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72644 nan -92.7439 -5.72644 0 0 0.13 -1 -1 75.3 MiB 0.25 0.223627 0.205422 31.2 MiB -1 0.04 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.64 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 130 9 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 77064 9 19 896 28 0 660 163 16 16 256 -1 mcnc_medium -1 -1 7727.83 7087 9508 603 6937 1968 75.3 MiB 2.09 0.00 6.3343 5.39115 -88.0884 -5.39115 nan 0.00 0.00133719 0.00116801 0.0488072 0.0445052 75.3 MiB 2.09 75.3 MiB 1.41 11108 16.8558 2920 4.43096 4709 24240 778883 128039 1.05632e+07 7.27569e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72644 nan -92.7439 -5.72644 0 0 0.13 -1 -1 75.3 MiB 0.25 0.223627 0.205422 31.2 MiB -1 0.04 k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.54 vpr 76.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 173 256 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 78236 256 245 954 501 0 760 674 22 22 484 -1 mcnc_large -1 -1 9292.95 7827 56800 1790 18880 36130 76.4 MiB 1.08 0.01 5.23911 4.45825 -854.38 -4.45825 nan 0.00 0.00195959 0.0018456 0.0499366 0.0472422 76.4 MiB 1.08 76.4 MiB 0.81 11106 14.6132 3086 4.06053 2658 7145 291226 67335 2.15576e+07 9.32366e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.93512 nan -901.874 -4.93512 0 0 0.15 -1 -1 76.4 MiB 0.16 0.143878 0.136836 33.7 MiB -1 0.05 k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.76 vpr 76.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 147 41 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 78320 41 35 1006 76 0 714 223 16 16 256 -1 mcnc_medium -1 -1 9169.27 7694 8335 415 5173 2747 76.5 MiB 2.20 0.01 6.36629 5.23793 -151.219 -5.23793 nan 0.00 0.0015282 0.00132775 0.0366109 0.0336215 76.5 MiB 2.20 76.5 MiB 1.46 12142 17.0056 3244 4.54342 4212 22271 689032 117413 1.05632e+07 7.92242e+06 1.26944e+06 4958.75 16 28900 206586 -1 5.65269 nan -156.023 -5.65269 0 0 0.13 -1 -1 76.5 MiB 0.24 0.22311 0.205529 31.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 6882f91309..324e7c41e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -2,4 +2,4 @@ k4_n4_v7_bidir.xml styr.blif common 1.37 vpr 62.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64104 10 10 253 263 1 171 92 11 11 121 clb auto 23.5 MiB 0.04 1829.24 1329 4646 728 3820 98 62.6 MiB 0.05 0.00 8.75156 5.65828 -74.3763 -5.65828 5.65828 0.08 0.000539066 0.000438929 0.0158895 0.0133045 -1 -1 -1 -1 14 1972 27 2.43e+06 2.16e+06 -1 -1 0.65 0.146019 0.12287 3402 27531 -1 1970 16 1168 4226 219209 27455 7.33108 7.33108 -92.5065 -7.33108 0 0 -1 -1 0.01 0.07 0.02 -1 -1 0.01 0.0241699 0.0213263 k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 63.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64704 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1305 3404 389 2964 51 63.2 MiB 0.04 0.00 5.19817 4.46893 -53.8773 -4.46893 4.46893 0.09 0.000510361 0.000414222 0.0114433 0.00959255 -1 -1 -1 -1 18 2312 35 2.43e+06 2.16e+06 -1 -1 1.02 0.19335 0.161505 3282 34431 -1 2326 21 1300 4425 297597 37882 9.34193 9.34193 -107.688 -9.34193 0 0 -1 -1 0.02 0.09 0.03 -1 -1 0.02 0.0293867 0.0256624 k4_n4_v7_l1_bidir.xml styr.blif common 1.82 vpr 62.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64084 10 10 253 263 1 171 92 11 11 121 clb auto 23.7 MiB 0.04 1829.24 1283 8993 1996 6843 154 62.6 MiB 0.10 0.00 11.3865 6.82489 -85.7025 -6.82489 6.82489 0.10 0.000535759 0.000437145 0.0267342 0.0222548 -1 -1 -1 -1 10 1437 37 2.43e+06 2.16e+06 -1 -1 0.95 0.1205 0.101293 4482 22551 -1 1348 24 1290 4977 336418 74151 8.81482 8.81482 -100.507 -8.81482 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0332838 0.0290833 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -323.027 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -315 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index 234512db02..c9c3140df6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.24 vpr 60.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62116 1 4 28 32 2 10 9 4 4 16 clb auto 22.1 MiB 0.00 22 21 774 371 276 127 60.7 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.7321e-05 3.993e-05 0.00449915 0.00382008 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0106069 0.00872526 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00169671 0.00154408 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.24 vpr 61.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62496 1 4 28 32 2 10 9 4 4 16 clb auto 22.3 MiB 0.00 22 21 774 371 276 127 61.0 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 5.5515e-05 4.7432e-05 0.00516991 0.0044429 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.0115274 0.00951085 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00167376 0.00152137 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.24 vpr 60.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14013-ge1496c441d release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-10-06T15:12:57 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong 62372 1 4 28 32 2 10 9 4 4 16 clb auto 22.3 MiB 0.00 22 21 774 371 276 127 60.9 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.8008e-05 4.0427e-05 0.0044909 0.00380767 -1 -1 -1 -1 6 20 5 72000 72000 4025.56 251.598 0.02 0.010696 0.00880945 660 1032 -1 13 6 19 19 358 106 2.39113 2.39113 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00173292 0.00158056 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.31 vpr 59.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14410-g2298aeccf-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-20T13:15:33 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 60656 1 4 28 32 2 10 9 4 4 16 clb auto 19.6 MiB 0.01 22 21 873 428 311 134 59.2 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 2.458e-05 1.572e-05 0.00273353 0.0018351 -1 -1 -1 -1 8 13 5 72000 72000 5593.62 349.601 0.02 0.00613828 0.00449115 672 1128 -1 13 7 21 21 407 128 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00116253 0.00102398 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.35 vpr 59.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14410-g2298aeccf-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-20T13:15:33 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 60716 1 4 28 32 2 10 9 4 4 16 clb auto 20.0 MiB 0.01 22 21 873 428 311 134 59.3 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 3.2544e-05 2.1892e-05 0.00353219 0.00246357 -1 -1 -1 -1 8 13 5 72000 72000 5593.62 349.601 0.03 0.00883382 0.00661421 672 1128 -1 13 7 21 21 407 128 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00137061 0.00120949 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.34 vpr 59.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-14410-g2298aeccf-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-20T13:15:33 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 60744 1 4 28 32 2 10 9 4 4 16 clb auto 19.9 MiB 0.01 22 21 873 428 311 134 59.3 MiB 0.01 0.00 2.44626 2.44626 0 0 2.44626 0.01 3.1359e-05 2.1167e-05 0.00343982 0.00239892 -1 -1 -1 -1 8 13 5 72000 72000 5593.62 349.601 0.03 0.00864508 0.00649589 672 1128 -1 13 7 21 21 407 128 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00132596 0.00114927 From 6094a6fe1987b6846440a62dbb9d64015471c63e Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 20 Nov 2025 14:36:55 -0800 Subject: [PATCH 08/13] [ci] update strong_custom_grid strong_sdc strong_soft_multipliers --- .../vtr_reg_strong/strong_custom_grid/config/golden_results.txt | 2 +- .../vtr_reg_strong/strong_sdc/config/golden_results.txt | 2 +- .../strong_soft_multipliers/config/golden_results.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index 3beb6c1013..f8edfed744 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -5,4 +5,4 @@ non_column_tall_aspect_ratio.xml raygentop.v common 17.71 vpr 99.84 MiB -1 -1 2.18 42720 4 0.55 -1 -1 36960 -1 -1 129 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 102236 236 305 3170 2982 1 1517 677 23 46 1058 io auto 47.8 MiB 2.03 36972 13791 238357 78620 131581 28156 96.5 MiB 1.13 0.02 8.28835 4.82201 -2889.55 -4.82201 4.82201 0.99 0.00478733 0.004413 0.430224 0.390576 -1 -1 -1 -1 52 27780 44 5.05849e+07 9.87633e+06 3.17293e+06 2998.99 6.59 1.81522 1.64979 97261 632982 -1 23254 19 7012 18758 1829454 483193 5.63042 5.63042 -3129.27 -5.63042 0 0 4.15960e+06 3931.57 0.16 0.59 0.52 -1 -1 0.16 0.281399 0.264065 non_column_wide_aspect_ratio.xml raygentop.v common 18.75 vpr 114.70 MiB -1 -1 2.12 41948 4 0.57 -1 -1 36956 -1 -1 129 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 117448 236 305 3170 2982 1 1517 677 53 27 1431 io auto 47.8 MiB 2.10 40311.6 16087 300748 105018 149649 46081 114.7 MiB 1.42 0.02 7.83521 4.85182 -3052.38 -4.85182 4.85182 1.51 0.0047411 0.00435747 0.556583 0.504699 -1 -1 -1 -1 48 30604 34 7.18852e+07 9.87633e+06 3.96130e+06 2768.20 6.13 1.80378 1.64019 126813 766723 -1 25771 17 6698 17200 1592529 406246 4.99409 4.99409 -3278.31 -4.99409 0 0 5.06025e+06 3536.17 0.20 0.55 0.62 -1 -1 0.20 0.263761 0.248281 custom_sbloc.xml raygentop.v common 12.79 vpr 84.70 MiB -1 -1 1.92 42344 4 0.56 -1 -1 36704 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 86732 236 305 3177 2989 1 1517 675 19 19 361 io clb auto 45.9 MiB 1.96 26256.7 13231 237395 72213 160216 4966 84.7 MiB 1.21 0.02 6.16993 4.60407 -2878.58 -4.60407 4.60407 0.25 0.0057112 0.0049104 0.452496 0.410913 -1 -1 -1 -1 64 24087 40 1.65001e+07 9.76854e+06 1.19565e+06 3312.06 4.18 1.81435 1.65742 35881 230269 -1 20668 19 6125 17534 1714638 444346 4.91417 4.91417 -3127.09 -4.91417 0 0 1.50465e+06 4168.01 0.04 0.56 0.17 -1 -1 0.04 0.285497 0.26822 - multiple_io_types.xml raygentop.v common 77.66 vpr 510.52 MiB -1 -1 2.06 41948 4 0.57 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 522768 236 305 3177 2989 1 1517 675 70 70 4900 io_left auto 45.9 MiB 2.63 80208.6 29491 101281 4797 30435 66049 510.5 MiB 0.61 0.02 10.9706 4.81705 -3822.69 -4.81705 4.81705 14.17 0.00530076 0.00468624 0.256582 0.234179 -1 -1 -1 -1 46 43945 30 2.76175e+08 9.76854e+06 1.25363e+07 2558.43 47.93 2.35081 2.15011 425698 2387761 -1 40421 17 8256 21235 3275501 821072 5.13584 5.13584 -4142.28 -5.13584 0 0 1.61910e+07 3304.29 0.59 0.68 1.69 -1 -1 0.59 0.21718 0.204926 + multiple_io_types.xml raygentop.v common 77.66 vpr 510.52 MiB -1 -1 2.06 41948 4 0.57 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 522768 236 305 3177 2989 1 1517 675 70 70 4900 io_left auto 45.9 MiB 2.63 80208.6 29491 101281 4797 30435 66049 510.5 MiB 0.61 0.02 10.9706 4.81705 -3822.69 -4.81705 4.81705 14.17 0.00530076 0.00468624 0.256582 0.234179 -1 -1 -1 -1 50 43945 30 2.76175e+08 9.76854e+06 1.65363e+07 3000 47.93 2.35081 2.15011 425698 2387761 -1 40421 17 8256 21235 3275501 821072 5.13584 5.13584 -4142.28 -5.13584 0 0 1.61910e+07 3304.29 0.59 0.68 1.69 -1 -1 0.59 0.21718 0.204926 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 7e8ad6cd5f..b35dc49402 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -2,6 +2,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem e k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.33 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 65864 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 20 810 394 244 172 64.3 MiB 0.01 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 1.6912e-05 1.2942e-05 0.00147502 0.0011356 -1 -1 -1 -1 8 11 2 107788 107788 4794.78 299.674 0.01 0.00385336 0.00308828 564 862 -1 18 4 13 13 372 218 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00112501 0.00105222 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.36 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 65864 5 3 11 14 2 9 10 4 4 16 clb auto 25.7 MiB 0.00 22 20 870 405 235 230 64.3 MiB 0.01 0.00 0.571 0.571 0 0 0.571 0.00 1.5939e-05 1.2321e-05 0.00150516 0.00117684 -1 -1 -1 -1 8 17 4 107788 107788 4794.78 299.674 0.01 0.00385582 0.00312068 564 862 -1 17 4 12 12 252 131 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00115165 0.00109399 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.36 vpr 63.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 65172 5 3 11 14 2 9 10 4 4 16 clb auto 25.4 MiB 0.00 22 21 620 285 242 93 63.6 MiB 0.01 0.00 0.646297 0.645978 -2.18969 -0.645978 0.571 0.00 2.1955e-05 1.4371e-05 0.00139068 0.000987622 -1 -1 -1 -1 6 21 8 107788 107788 3417.33 213.583 0.01 0.00303703 0.00241011 552 802 -1 20 8 24 24 508 283 0.59309 0.571 -2.01015 -0.59309 0 0 4794.78 299.674 0.00 0.00 0.00 -1 -1 0.00 0.00121673 0.00111335 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.35 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 65864 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 20 670 310 248 112 64.3 MiB 0.01 0.00 1.64604 1.6463 -5.31901 -1.6463 0.571 0.01 1.912e-05 1.4412e-05 0.00149794 0.00105011 -1 -1 -1 -1 8 34 15 107788 107788 4794.78 299.674 0.02 0.00465997 0.00346962 564 862 -1 24 3 10 10 284 182 1.57153 0.571 -5.24124 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00118015 0.00110489 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.35 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 65864 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 20 670 310 248 112 64.3 MiB 0.01 0.00 1.64604 1.6463 -5.31901 -1.6463 0.571 0.01 1.912e-05 1.4412e-05 0.00149794 0.00105011 -1 -1 -1 -1 8 20 15 107788 107788 4794.78 299.674 0.02 0.00465997 0.00346962 564 862 -1 24 3 10 10 284 182 1.57153 0.571 -5.24124 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00118015 0.00110489 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.36 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 65864 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 20 200 38 110 52 64.3 MiB 0.00 0.00 1.44967 1.44871 -2.90935 -1.44871 0.571 0.00 1.9113e-05 1.4835e-05 0.000521838 0.000397098 -1 -1 -1 -1 6 26 6 107788 107788 3417.33 213.583 0.01 0.00248721 0.00203975 552 802 -1 15 20 48 48 1206 797 1.56638 0.571 -2.99759 -1.56638 0 0 4794.78 299.674 0.00 0.00 0.00 -1 -1 0.00 0.00163147 0.00142426 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.35 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 65864 5 3 11 14 2 9 10 4 4 16 clb auto 25.5 MiB 0.00 22 20 530 219 169 142 64.3 MiB 0.00 0.00 0.146298 0.145978 0 0 0.571 0.00 1.8195e-05 1.4207e-05 0.00111733 0.000861244 -1 -1 -1 -1 6 20 4 107788 107788 3417.33 213.583 0.01 0.00244519 0.00206485 552 802 -1 17 2 11 11 260 139 0.0715255 0.571 0 0 0 0 4794.78 299.674 0.00 0.00 0.00 -1 -1 0.00 0.00110375 0.00104728 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index e76a36f488..8b5f6c1512 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.19 vpr 65.16 MiB -1 -1 0.07 19956 1 0.02 -1 -1 29816 -1 -1 3 9 0 -1 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 66724 9 8 75 70 1 34 20 5 5 25 clb auto 26.4 MiB 0.43 116 85 1586 677 891 18 65.2 MiB 0.01 0.00 2.64007 2.48207 -26.0196 -2.48207 2.48207 0.01 9.5705e-05 8.6339e-05 0.00623502 0.00564291 -1 -1 -1 -1 26 239 17 151211 75605.7 37105.9 1484.24 0.08 0.0290937 0.0246362 1908 5841 -1 135 7 92 95 2945 1656 2.87707 2.87707 -32.3084 -2.87707 0 0 45067.1 1802.68 0.00 0.01 0.00 -1 -1 0.00 0.00407687 0.00381433 13 18 -1 -1 -1 -1 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.52 vpr 65.32 MiB -1 -1 0.07 19952 1 0.02 -1 -1 29716 -1 -1 2 11 0 -1 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 66884 11 10 108 97 1 48 23 4 4 16 clb auto 26.4 MiB 1.72 145.745 128 2583 1037 1310 236 65.3 MiB 0.02 0.00 3.45122 3.45122 -42.3331 -3.45122 3.45122 0.01 0.000128796 0.000116897 0.0111285 0.0101435 -1 -1 -1 -1 32 219 32 50403.8 50403.8 20844.1 1302.76 0.13 0.0553907 0.0468214 1004 2840 -1 164 11 159 229 6534 4021 3.40193 3.40193 -47.6211 -3.40193 0 0 24991.0 1561.94 0.00 0.01 0.00 -1 -1 0.00 0.00620027 0.00573623 14 27 -1 -1 -1 -1 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.26 vpr 65.61 MiB -1 -1 0.08 20336 1 0.03 -1 -1 29756 -1 -1 7 13 0 -1 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 67184 13 12 149 129 1 68 32 6 6 36 clb auto 26.0 MiB 3.21 259.236 199 3832 1568 2180 84 65.6 MiB 0.03 0.00 3.49758 3.49758 -52.5769 -3.49758 3.49758 0.02 0.000163585 0.000148802 0.0144768 0.0132395 -1 -1 -1 -1 32 632 26 403230 176413 76028.0 2111.89 0.28 0.0826928 0.0704016 3558 13169 -1 364 17 325 417 15525 7118 3.73458 3.73458 -60.4166 -3.73458 0 0 91794.1 2549.84 0.00 0.02 0.01 -1 -1 0.00 0.00968311 0.00882127 25 38 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.26 vpr 65.61 MiB -1 -1 0.08 20336 1 0.03 -1 -1 29756 -1 -1 7 13 0 -1 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 67184 13 12 149 129 1 68 32 6 6 36 clb auto 26.0 MiB 3.21 259.236 199 3832 1568 2180 84 65.6 MiB 0.03 0.00 3.49758 3.49758 -52.5769 -3.49758 3.49758 0.02 0.000163585 0.000148802 0.0144768 0.0132395 -1 -1 -1 -1 32 366 26 403230 176413 76028.0 2111.89 0.28 0.0826928 0.0704016 3558 13169 -1 364 17 325 417 15525 7118 3.73458 3.73458 -60.4166 -3.73458 0 0 91794.1 2549.84 0.00 0.02 0.01 -1 -1 0.00 0.00968311 0.00882127 25 38 -1 -1 -1 -1 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.52 vpr 65.54 MiB -1 -1 0.08 19952 1 0.02 -1 -1 29812 -1 -1 7 15 0 -1 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 67108 15 14 196 165 1 92 36 6 6 36 clb auto 26.2 MiB 1.55 339.362 305 4815 1886 2816 113 65.5 MiB 0.03 0.00 3.66013 3.62628 -64.9445 -3.62628 3.62628 0.02 0.000208928 0.000190215 0.0192218 0.0176042 -1 -1 -1 -1 52 608 18 403230 176413 110337. 3064.92 0.15 0.0649109 0.0567048 4014 20275 -1 491 16 415 588 18860 7886 4.11059 4.11059 -72.9556 -4.11059 0 0 143382. 3982.83 0.00 0.02 0.01 -1 -1 0.00 0.0114056 0.010459 37 51 -1 -1 -1 -1 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 5.42 vpr 66.14 MiB -1 -1 0.07 19952 1 0.03 -1 -1 29860 -1 -1 5 17 0 -1 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 67724 17 16 251 206 1 117 38 5 5 25 clb auto 26.4 MiB 4.30 488.93 400 5834 2877 2918 39 66.1 MiB 0.05 0.00 3.8942 3.89124 -74.9686 -3.89124 3.89124 0.01 0.000259714 0.000237096 0.0275695 0.0252326 -1 -1 -1 -1 46 707 35 151211 126010 57775.2 2311.01 0.32 0.13291 0.114533 2220 9391 -1 558 21 663 1082 33018 15212 4.81406 4.81406 -96.0866 -4.81406 0 0 73020.3 2920.81 0.00 0.03 0.01 -1 -1 0.00 0.0163331 0.0148651 44 66 -1 -1 -1 -1 k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 5.22 vpr 66.48 MiB -1 -1 0.09 20720 1 0.03 -1 -1 29864 -1 -1 7 19 0 -1 success v8.0.0-14178-g4818739e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-71-generic x86_64 2025-10-15T12:13:40 betzgrp-wintermute /home/gholam39/vpr/vtr-verilog-to-routing/vtr_flow 68076 19 18 308 249 1 134 44 6 6 36 clb auto 26.8 MiB 3.92 669.263 458 5819 2415 3368 36 66.5 MiB 0.05 0.00 5.1706 4.8546 -99.6466 -4.8546 4.8546 0.02 0.000307933 0.00028155 0.0271862 0.0248985 -1 -1 -1 -1 40 1046 28 403230 176413 88484.8 2457.91 0.42 0.148944 0.128909 3734 16003 -1 796 20 753 1121 43775 19222 5.51164 5.51164 -119.88 -5.51164 0 0 110337. 3064.92 0.00 0.03 0.01 -1 -1 0.00 0.0188351 0.017201 53 83 -1 -1 -1 -1 From 918a10f14fcf6f8c0e63021e9dd2a796a1596e86 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Fri, 21 Nov 2025 06:23:52 -0800 Subject: [PATCH 09/13] [ci] update strong_bidir golden resutls --- .../vtr_reg_strong/strong_bidir/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 324e7c41e3..1b4f5e94b8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -2,4 +2,4 @@ k4_n4_v7_bidir.xml styr.blif common 1.37 vpr 62.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64104 10 10 253 263 1 171 92 11 11 121 clb auto 23.5 MiB 0.04 1829.24 1329 4646 728 3820 98 62.6 MiB 0.05 0.00 8.75156 5.65828 -74.3763 -5.65828 5.65828 0.08 0.000539066 0.000438929 0.0158895 0.0133045 -1 -1 -1 -1 14 1972 27 2.43e+06 2.16e+06 -1 -1 0.65 0.146019 0.12287 3402 27531 -1 1970 16 1168 4226 219209 27455 7.33108 7.33108 -92.5065 -7.33108 0 0 -1 -1 0.01 0.07 0.02 -1 -1 0.01 0.0241699 0.0213263 k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 63.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64704 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1305 3404 389 2964 51 63.2 MiB 0.04 0.00 5.19817 4.46893 -53.8773 -4.46893 4.46893 0.09 0.000510361 0.000414222 0.0114433 0.00959255 -1 -1 -1 -1 18 2312 35 2.43e+06 2.16e+06 -1 -1 1.02 0.19335 0.161505 3282 34431 -1 2326 21 1300 4425 297597 37882 9.34193 9.34193 -107.688 -9.34193 0 0 -1 -1 0.02 0.09 0.03 -1 -1 0.02 0.0293867 0.0256624 k4_n4_v7_l1_bidir.xml styr.blif common 1.82 vpr 62.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64084 10 10 253 263 1 171 92 11 11 121 clb auto 23.7 MiB 0.04 1829.24 1283 8993 1996 6843 154 62.6 MiB 0.10 0.00 11.3865 6.82489 -85.7025 -6.82489 6.82489 0.10 0.000535759 0.000437145 0.0267342 0.0222548 -1 -1 -1 -1 10 1437 37 2.43e+06 2.16e+06 -1 -1 0.95 0.1205 0.101293 4482 22551 -1 1348 24 1290 4977 336418 74151 8.81482 8.81482 -100.507 -8.81482 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0332838 0.0290833 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -315 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -260 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146 From 07e78a7def10448c068e64a74dc80abf37cb3f89 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Fri, 21 Nov 2025 12:30:05 -0800 Subject: [PATCH 10/13] [ci] update strong flat router --- .../strong_flat_router/config/golden_results.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index 5254889535..b46cafdaff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.66 vpr 79.59 MiB -1 -1 1.82 32820 16 0.42 -1 -1 34360 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 81504 45 32 1201 1160 1 783 144 14 14 196 memory auto 41.5 MiB 1.69 9983.95 6837 19748 5148 14340 260 79.6 MiB 0.28 0.01 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00210698 0.0018731 0.13099 0.115486 -1 -1 -1 -1 10382 8.66611 2740 2.28715 3140 14798 1339040 147684 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 16 45716 406619 17417 11.6791 11.6791 -7715.01 -11.6791 0 0 0.13 0.64 0.52 79.6 MiB 1.17 0.200391 0.176279 79.6 MiB 0.12 0.03 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 8.96 vpr 79.13 MiB -1 -1 2.24 40220 16 0.66 -1 -1 38912 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81028 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.6 MiB 2.40 9983.95 6692 37844 15471 21756 617 79.1 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00160347 0.00131911 0.202487 0.163526 -1 -1 -1 -1 10360 8.64775 2786 2.32554 3277 16160 1513142 177862 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 13 52300 435073 15723 12.1565 12.1565 -7596.49 -12.1565 0 0 0.16 0.88 0.75 79.1 MiB 1.58 0.252699 0.205132 79.1 MiB 0.16 0.05 k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.64 vpr 79.19 MiB -1 -1 1.51 33588 16 0.43 -1 -1 34372 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 81088 45 32 1201 1160 1 783 144 14 14 196 memory auto 41.0 MiB 1.84 9983.95 6837 19748 5148 14340 260 79.2 MiB 0.29 0.01 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00222732 0.00189111 0.1317 0.109721 -1 -1 -1 -1 10443 8.71703 2750 2.29549 3161 15375 1392011 152666 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 12 45716 406619 17417 11.6791 11.6791 -7722.48 -11.6791 0 0 0.13 0.69 0.56 79.2 MiB 1.23 0.18425 0.153208 79.2 MiB 0.13 0.03 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 10.88 vpr 79.58 MiB -1 -1 1.72 32828 16 0.43 -1 -1 34368 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 81488 45 32 1201 1160 1 783 144 14 14 196 memory auto 41.4 MiB 1.68 9983.95 6837 19748 5148 14340 260 79.6 MiB 0.28 0.01 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00212171 0.00188597 0.133325 0.11809 -1 -1 -1 -1 10486 8.75292 2770 2.31219 2730 12935 12360712 12360712 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 12 45716 406619 17417 11.6724 11.6724 -7741.54 -11.6724 0 0 0.13 0.64 0.52 79.6 MiB 5.50 0.194193 0.171088 79.6 MiB 0.12 0.03 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 11.28 vpr 79.58 MiB -1 -1 1.64 32828 16 0.45 -1 -1 34376 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 81492 45 32 1201 1160 1 783 144 14 14 196 memory auto 41.3 MiB 1.77 9983.95 6837 19748 5148 14340 260 79.6 MiB 0.29 0.01 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00244582 0.00220781 0.137178 0.121982 -1 -1 -1 -1 10486 8.75292 2770 2.31219 2730 12935 12521019 12521019 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 12 45716 406619 17417 11.6724 11.6724 -7741.54 -11.6724 0 0 0.12 0.82 0.69 79.6 MiB 5.81 0.200647 0.177977 79.6 MiB 0.13 0.03 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.17 vpr 78.88 MiB -1 -1 1.49 33600 16 0.43 -1 -1 34372 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 80772 45 32 1201 1160 1 783 144 14 14 196 memory auto 40.7 MiB 1.72 9983.95 6837 19748 5148 14340 260 78.9 MiB 0.27 0.00 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00192149 0.00169201 0.122653 0.108032 -1 -1 -1 -1 10486 8.75292 2770 2.31219 2730 12935 12702465 5662306 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 12 45716 406619 17417 11.6724 11.6724 -7741.54 -11.6724 0 0 0.12 0.64 0.52 78.9 MiB 3.96 0.180729 0.15881 78.9 MiB 0.12 0.03 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 14.54 vpr 80.91 MiB -1 -1 2.24 40172 16 0.62 -1 -1 39116 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 82856 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.4 MiB 2.49 9983.95 6692 37844 15471 21756 617 80.9 MiB 0.61 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00157343 0.00129122 0.221411 0.180035 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13089801 13089801 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.84 0.71 80.9 MiB 7.10 0.265811 0.216934 80.9 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 13.60 vpr 79.29 MiB -1 -1 2.19 40396 16 0.61 -1 -1 39024 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81192 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.8 MiB 2.47 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.65 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00158864 0.00127712 0.240684 0.197275 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13246702 13246702 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.73 79.3 MiB 6.15 0.281592 0.231452 79.3 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 12.49 vpr 79.27 MiB -1 -1 2.32 40376 16 0.60 -1 -1 39204 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81172 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.7 MiB 2.32 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00153685 0.00125038 0.210247 0.171409 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13409513 6279917 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.74 79.3 MiB 5.17 0.256961 0.210528 79.3 MiB 0.15 0.05 From 208c42b2d36b03c0f8207cf5a1164011e13fecb0 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Fri, 21 Nov 2025 13:17:03 -0800 Subject: [PATCH 11/13] [ci] get flat router ci results from ci --- .../strong_flat_router/config/golden_results.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index b46cafdaff..460042951f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 8.96 vpr 79.13 MiB -1 -1 2.24 40220 16 0.66 -1 -1 38912 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81028 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.6 MiB 2.40 9983.95 6692 37844 15471 21756 617 79.1 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00160347 0.00131911 0.202487 0.163526 -1 -1 -1 -1 10360 8.64775 2786 2.32554 3277 16160 1513142 177862 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 13 52300 435073 15723 12.1565 12.1565 -7596.49 -12.1565 0 0 0.16 0.88 0.75 79.1 MiB 1.58 0.252699 0.205132 79.1 MiB 0.16 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.64 vpr 79.19 MiB -1 -1 1.51 33588 16 0.43 -1 -1 34372 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 81088 45 32 1201 1160 1 783 144 14 14 196 memory auto 41.0 MiB 1.84 9983.95 6837 19748 5148 14340 260 79.2 MiB 0.29 0.01 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00222732 0.00189111 0.1317 0.109721 -1 -1 -1 -1 10443 8.71703 2750 2.29549 3161 15375 1392011 152666 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 12 45716 406619 17417 11.6791 11.6791 -7722.48 -11.6791 0 0 0.13 0.69 0.56 79.2 MiB 1.23 0.18425 0.153208 79.2 MiB 0.13 0.03 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 14.54 vpr 80.91 MiB -1 -1 2.24 40172 16 0.62 -1 -1 39116 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 82856 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.4 MiB 2.49 9983.95 6692 37844 15471 21756 617 80.9 MiB 0.61 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00157343 0.00129122 0.221411 0.180035 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13089801 13089801 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.84 0.71 80.9 MiB 7.10 0.265811 0.216934 80.9 MiB 0.15 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 13.60 vpr 79.29 MiB -1 -1 2.19 40396 16 0.61 -1 -1 39024 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81192 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.8 MiB 2.47 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.65 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00158864 0.00127712 0.240684 0.197275 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13246702 13246702 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.73 79.3 MiB 6.15 0.281592 0.231452 79.3 MiB 0.15 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 12.49 vpr 79.27 MiB -1 -1 2.32 40376 16 0.60 -1 -1 39204 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81172 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.7 MiB 2.32 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00153685 0.00125038 0.210247 0.171409 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13409513 6279917 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.74 79.3 MiB 5.17 0.256961 0.210528 79.3 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From c57c1f84957448ae59fd36139bc5262956fc1466 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Fri, 21 Nov 2025 13:53:48 -0800 Subject: [PATCH 12/13] Revert "[ci] get flat router ci results from ci" This reverts commit 208c42b2d36b03c0f8207cf5a1164011e13fecb0. --- .../strong_flat_router/config/golden_results.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index 460042951f..b46cafdaff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 unknown unknown unknown unknown -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 8.96 vpr 79.13 MiB -1 -1 2.24 40220 16 0.66 -1 -1 38912 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81028 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.6 MiB 2.40 9983.95 6692 37844 15471 21756 617 79.1 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00160347 0.00131911 0.202487 0.163526 -1 -1 -1 -1 10360 8.64775 2786 2.32554 3277 16160 1513142 177862 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 13 52300 435073 15723 12.1565 12.1565 -7596.49 -12.1565 0 0 0.16 0.88 0.75 79.1 MiB 1.58 0.252699 0.205132 79.1 MiB 0.16 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.64 vpr 79.19 MiB -1 -1 1.51 33588 16 0.43 -1 -1 34372 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 81088 45 32 1201 1160 1 783 144 14 14 196 memory auto 41.0 MiB 1.84 9983.95 6837 19748 5148 14340 260 79.2 MiB 0.29 0.01 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00222732 0.00189111 0.1317 0.109721 -1 -1 -1 -1 10443 8.71703 2750 2.29549 3161 15375 1392011 152666 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 12 45716 406619 17417 11.6791 11.6791 -7722.48 -11.6791 0 0 0.13 0.69 0.56 79.2 MiB 1.23 0.18425 0.153208 79.2 MiB 0.13 0.03 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 14.54 vpr 80.91 MiB -1 -1 2.24 40172 16 0.62 -1 -1 39116 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 82856 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.4 MiB 2.49 9983.95 6692 37844 15471 21756 617 80.9 MiB 0.61 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00157343 0.00129122 0.221411 0.180035 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13089801 13089801 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.84 0.71 80.9 MiB 7.10 0.265811 0.216934 80.9 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 13.60 vpr 79.29 MiB -1 -1 2.19 40396 16 0.61 -1 -1 39024 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81192 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.8 MiB 2.47 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.65 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00158864 0.00127712 0.240684 0.197275 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13246702 13246702 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.73 79.3 MiB 6.15 0.281592 0.231452 79.3 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 12.49 vpr 79.27 MiB -1 -1 2.32 40376 16 0.60 -1 -1 39204 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81172 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.7 MiB 2.32 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00153685 0.00125038 0.210247 0.171409 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13409513 6279917 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.74 79.3 MiB 5.17 0.256961 0.210528 79.3 MiB 0.15 0.05 From ecc8cfe8f0c60cc71cff5d861774e1c876fc8e26 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Fri, 21 Nov 2025 14:04:11 -0800 Subject: [PATCH 13/13] [ci] update golden results --- .../strong_flat_router/config/golden_results.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index b46cafdaff..8b5c5140f3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 8.96 vpr 79.13 MiB -1 -1 2.24 40220 16 0.66 -1 -1 38912 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81028 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.6 MiB 2.40 9983.95 6692 37844 15471 21756 617 79.1 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00160347 0.00131911 0.202487 0.163526 -1 -1 -1 -1 10360 8.64775 2786 2.32554 3277 16160 1513142 177862 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 13 52300 435073 15723 12.1565 12.1565 -7596.49 -12.1565 0 0 0.16 0.88 0.75 79.1 MiB 1.58 0.252699 0.205132 79.1 MiB 0.16 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 8.96 vpr 79.13 MiB -1 -1 2.24 40220 16 0.66 -1 -1 38912 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81028 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.6 MiB 2.40 9983.95 6692 37844 15471 21756 617 79.1 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00160347 0.00131911 0.202487 0.163526 -1 -1 -1 -1 10360 8.64775 2786 2.32554 3277 16160 1513142 177862 9.20055e+06 5.43532e+06 1.3363e+06 6817.9 13 52300 435073 15723 12.1565 12.1565 -7596.49 -12.1565 0 0 0.16 0.88 0.75 79.1 MiB 1.58 0.252699 0.205132 79.1 MiB 0.16 0.05 k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.64 vpr 79.19 MiB -1 -1 1.51 33588 16 0.43 -1 -1 34372 -1 -1 63 45 3 1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 81088 45 32 1201 1160 1 783 144 14 14 196 memory auto 41.0 MiB 1.84 9983.95 6837 19748 5148 14340 260 79.2 MiB 0.29 0.01 13.1759 11.4387 -7248.38 -11.4387 11.4387 0.00 0.00222732 0.00189111 0.1317 0.109721 -1 -1 -1 -1 10443 8.71703 2750 2.29549 3161 15375 1392011 152666 9.20055e+06 5.43532e+06 1.47691e+06 7535.23 12 45716 406619 17417 11.6791 11.6791 -7722.48 -11.6791 0 0 0.13 0.69 0.56 79.2 MiB 1.23 0.18425 0.153208 79.2 MiB 0.13 0.03 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 14.54 vpr 80.91 MiB -1 -1 2.24 40172 16 0.62 -1 -1 39116 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 82856 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.4 MiB 2.49 9983.95 6692 37844 15471 21756 617 80.9 MiB 0.61 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00157343 0.00129122 0.221411 0.180035 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13089801 13089801 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.84 0.71 80.9 MiB 7.10 0.265811 0.216934 80.9 MiB 0.15 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 13.60 vpr 79.29 MiB -1 -1 2.19 40396 16 0.61 -1 -1 39024 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81192 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.8 MiB 2.47 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.65 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00158864 0.00127712 0.240684 0.197275 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13246702 13246702 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.73 79.3 MiB 6.15 0.281592 0.231452 79.3 MiB 0.15 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 12.49 vpr 79.27 MiB -1 -1 2.32 40376 16 0.60 -1 -1 39204 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81172 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.7 MiB 2.32 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00153685 0.00125038 0.210247 0.171409 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13409513 6279917 9.20055e+06 5.43532e+06 1.11359e+06 5681.59 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.74 79.3 MiB 5.17 0.256961 0.210528 79.3 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 14.54 vpr 80.91 MiB -1 -1 2.24 40172 16 0.62 -1 -1 39116 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 82856 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.4 MiB 2.49 9983.95 6692 37844 15471 21756 617 80.9 MiB 0.61 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00157343 0.00129122 0.221411 0.180035 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13089801 13089801 9.20055e+06 5.43532e+06 1.3363e+06 6817.9 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.84 0.71 80.9 MiB 7.10 0.265811 0.216934 80.9 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 13.60 vpr 79.29 MiB -1 -1 2.19 40396 16 0.61 -1 -1 39024 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81192 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.8 MiB 2.47 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.65 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00158864 0.00127712 0.240684 0.197275 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13246702 13246702 9.20055e+06 5.43532e+06 1.3363e+06 6817.9 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.73 79.3 MiB 6.15 0.281592 0.231452 79.3 MiB 0.15 0.05 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 12.49 vpr 79.27 MiB -1 -1 2.32 40376 16 0.60 -1 -1 39204 -1 -1 63 45 3 1 success v8.0.0-14428-g10a876a90-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-5.4.0-216-generic x86_64 2025-11-21T09:41:47 qlsof01.quicklogic.com /dsoft/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 81172 45 32 1201 1160 1 783 144 14 14 196 memory auto 42.7 MiB 2.32 9983.95 6692 37844 15471 21756 617 79.3 MiB 0.58 0.01 13.1759 11.6025 -7102.21 -11.6025 11.6025 0.00 0.00153685 0.00125038 0.210247 0.171409 -1 -1 -1 -1 10231 8.54007 2767 2.30968 2774 13435 13409513 6279917 9.20055e+06 5.43532e+06 1.3363e+06 6817.9 10 52300 435073 15723 12.1042 12.1042 -7532.57 -12.1042 0 0 0.15 0.87 0.74 79.3 MiB 5.17 0.256961 0.210528 79.3 MiB 0.15 0.05