diff --git a/indent/verilog_systemverilog.vim b/indent/verilog_systemverilog.vim index 91fa051..d1dd35e 100644 --- a/indent/verilog_systemverilog.vim +++ b/indent/verilog_systemverilog.vim @@ -358,6 +358,15 @@ function! s:GetContextIndent() if l:bracket_level < 0 call verilog_systemverilog#Verbose("Inside a '()' block.") return indent(l:lnum) + s:offset + elseif l:bracket_level > 0 + call verilog_systemverilog#Verbose("Inside a '()' block. Skipping the whole block.") + while l:bracket_level > 0 + let l:lnum = s:SearchForBlockStart('(', '', ')', l:lnum, 0) + let l:line = s:GetLineStripped(l:lnum) + let l:bracket_level += + \ s:CountMatches(l:line, ')') - s:CountMatches(l:line, '(') + endwhile + call verilog_systemverilog#Verbose("End of '()' block found at line " . l:lnum . ".") endif endif @@ -367,6 +376,15 @@ function! s:GetContextIndent() if l:cbracket_level < 0 call verilog_systemverilog#Verbose("Inside a '{}' block.") return indent(l:lnum) + s:offset + l:open_offset + elseif l:cbracket_level > 0 + call verilog_systemverilog#Verbose("Inside a '{}' block. Skipping the whole block.") + while l:cbracket_level > 0 + let l:lnum = s:SearchForBlockStart('{', '', '}', l:lnum, 0) + let l:line = s:GetLineStripped(l:lnum) + let l:cbracket_level += + \ s:CountMatches(l:line, '}') - s:CountMatches(l:line, '{') + endwhile + call verilog_systemverilog#Verbose("End of '{}' block found at line " . l:lnum . ".") endif endif diff --git a/test/indent.sv b/test/indent.sv index 4771e0c..f6ed3c7 100644 --- a/test/indent.sv +++ b/test/indent.sv @@ -1079,4 +1079,23 @@ package automatic regmodel_dpi_pkg; endpackage // End of copied code +// Code from: // https://github.com/vhda/verilog_systemverilog.vim/issues/231 +class my_class; + + int my_var; + + constraint reg_addr_c { + `ifndef MY_MACRO + my_var == 2; + `else + my_var == 3; + `endif + } + + function new(); + endfunction + +endclass +// End of copied code + // vi: set expandtab softtabstop=4 shiftwidth=4: diff --git a/test/indent.sv.html b/test/indent.sv.html index 3649870..5e1fea5 100644 --- a/test/indent.sv.html +++ b/test/indent.sv.html @@ -1081,6 +1081,25 @@ endpackage // End of copied code +// Code from: // https://github.com/vhda/verilog_systemverilog.vim/issues/231 +class my_class; + + int my_var; + + constraint reg_addr_c { + `ifndef MY_MACRO + my_var == 2; + `else + my_var == 3; + `endif + } + + function new(); + endfunction + +endclass +// End of copied code + // vi: set expandtab softtabstop=4 shiftwidth=4: