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65 | 65 | #define DMA_BUSY_CHECK
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66 | 66 | #endif
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67 | 67 |
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| 68 | +// Handle high performance MHS RPi display type |
| 69 | +#if defined (MHS_DISPLAY_TYPE) && !defined (RPI_DISPLAY_TYPE) |
| 70 | + #define RPI_DISPLAY_TYPE |
| 71 | +#endif |
| 72 | + |
68 | 73 | #if !defined (RP2040_PIO_INTERFACE) // SPI
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69 |
| - // Initialise processor specific SPI functions, used by init() |
70 |
| - #define INIT_TFT_DATA_BUS // Not used |
| 74 | + |
| 75 | + #if defined (MHS_DISPLAY_TYPE) // High speed RPi TFT type always needs 16 bit transfers |
| 76 | + // This swaps to 16 bit mode, used for commands so wait avoids clash with DC timing |
| 77 | + #define INIT_TFT_DATA_BUS hw_write_masked(&spi_get_hw(SPI_X)->cr0, (16 - 1) << SPI_SSPCR0_DSS_LSB, SPI_SSPCR0_DSS_BITS) |
| 78 | + #else |
| 79 | + // Initialise processor specific SPI functions, used by init() |
| 80 | + #define INIT_TFT_DATA_BUS // Not used |
| 81 | + #endif |
71 | 82 |
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72 | 83 | // Wait for tx to end, flush rx FIFO, clear rx overrun
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73 | 84 | #define SPI_BUSY_CHECK while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {}; \
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141 | 152 | #if !defined (RP2040_PIO_INTERFACE)// SPI
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142 | 153 | //#define DC_C sio_hw->gpio_clr = (1ul << TFT_DC)
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143 | 154 | //#define DC_D sio_hw->gpio_set = (1ul << TFT_DC)
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144 |
| - #if defined (RPI_DISPLAY_TYPE) |
| 155 | + #if defined (RPI_DISPLAY_TYPE) && !defined (MHS_DISPLAY_TYPE) |
145 | 156 | #define DC_C digitalWrite(TFT_DC, LOW);
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146 | 157 | #define DC_D digitalWrite(TFT_DC, HIGH);
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147 | 158 | #else
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167 | 178 | #define CS_H // No macro allocated so it generates no code
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168 | 179 | #else
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169 | 180 | #if !defined (RP2040_PIO_INTERFACE) // SPI
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170 |
| - #if defined (RPI_DISPLAY_TYPE) |
| 181 | + #if defined (RPI_DISPLAY_TYPE) && !defined (MHS_DISPLAY_TYPE) |
171 | 182 | #define CS_L digitalWrite(TFT_CS, LOW);
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172 | 183 | #define CS_H digitalWrite(TFT_CS, HIGH);
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173 | 184 | #else
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287 | 298 | // Macros to write commands/pixel colour data to other displays
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288 | 299 | ////////////////////////////////////////////////////////////////////////////////////////
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289 | 300 | #else
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290 |
| - #if defined (RPI_DISPLAY_TYPE) // RPi TFT type always needs 16 bit transfers |
| 301 | + #if defined (MHS_DISPLAY_TYPE) // High speed RPi TFT type always needs 16 bit transfers |
| 302 | + // This swaps to 16 bit mode, used for commands so wait avoids clash with DC timing |
| 303 | + #define tft_Write_8(C) while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {}; \ |
| 304 | + hw_write_masked(&spi_get_hw(SPI_X)->cr0, (16 - 1) << SPI_SSPCR0_DSS_LSB, SPI_SSPCR0_DSS_BITS); \ |
| 305 | + spi_get_hw(SPI_X)->dr = (uint32_t)((C) | ((C)<<8)); \ |
| 306 | + while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {}; \ |
| 307 | + |
| 308 | + // Note: the following macros do not wait for the end of transmission |
| 309 | + |
| 310 | + #define tft_Write_16(C) while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = (uint32_t)(C) |
| 311 | + |
| 312 | + #define tft_Write_16N(C) while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = (uint32_t)(C) |
| 313 | + |
| 314 | + #define tft_Write_16S(C) while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = (uint32_t)(C)<<8 | (C)>>8 |
| 315 | + |
| 316 | + #define tft_Write_32(C) spi_get_hw(SPI_X)->dr = (uint32_t)((C)>>16); spi_get_hw(SPI_X)->dr = (uint32_t)(C) |
| 317 | + |
| 318 | + #define tft_Write_32C(C,D) spi_get_hw(SPI_X)->dr = (uint32_t)(C); spi_get_hw(SPI_X)->dr = (uint32_t)(D) |
| 319 | + |
| 320 | + #define tft_Write_32D(C) spi_get_hw(SPI_X)->dr = (uint32_t)(C); spi_get_hw(SPI_X)->dr = (uint32_t)(C) |
| 321 | + |
| 322 | + #elif defined (RPI_DISPLAY_TYPE) // RPi TFT type always needs 16 bit transfers |
291 | 323 | #define tft_Write_8(C) spi.transfer(C); spi.transfer(C)
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292 | 324 | #define tft_Write_16(C) spi.transfer((uint8_t)((C)>>8));spi.transfer((uint8_t)((C)>>0))
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293 | 325 | #define tft_Write_16N(C) spi.transfer((uint8_t)((C)>>8));spi.transfer((uint8_t)((C)>>0))
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