p_clk should be shareable between RMII interfaces

[henkmuller]

On the dual Ethernet board we have a single p_clk pin for both PHYs.

The present interface does not cater for this

One way around this is to extract the setup code for the ports, so that the code can be invoked as follows::

on tile[0]: {
    rmii_setup(p_clk, read/write ports 0);
    rmii_setup(p_clk, read/write ports 1);
    par {
        rmii_interface(read/write ports 0);
        rmii_interface(read/write ports 1);
    }
}

[ed-xmos]

The other option is an unsafe port, but it;'s a bit messy

lib_ethernet/tests/bringup_xk_eth_xu316_dual_100m/src/main.xc

Line 100 in 28d1b03

unsafe port p_eth_clk;