Updated XS3/ai port timings do not work under simulation

[ed-xmos]

As part of applying the verified findings of Henk's appnote (and put into a PR) I found that applying the known-good hardware IO timings breaks the simulation.

Previously sim timings were already different which suggests the timing of the PHY model is already different from the hardware. They are quite significantly different - like 6 core clock cycles which is around 10ns.

So this issue covers whether we should re-visit the PHY model timing and see whether there is fundamentally a difference between xsim and hw which needs to be accommodated or whether we should make the XS3 phy timings match hardware.

[ed-xmos]

This is related to #270

[ed-xmos]

Having looked in more detail, it seems that the PHY sim model does things on the negedge whereas the PHY silicon launches data/control and samples on the posedge. Since we have highly optimised the port timing now on phoenix it means that the PHY model is causing the tx_ready strobe to be sampled too late by the xcore, causing the frame token to be sampled multiple times since the xcore doesn't present the data early enough.

This suggests that it is the simulation that needs fixing rather than the silicon timings.