WIP: removed modification of design object from within SbDut

Author: RiceShelley

python/switchboard_pybind.cc

@@ -639,7 +639,8 @@ class PyUmi {
     }
 
     py::array read(uint64_t addr, uint32_t num, size_t bytes_per_elem, uint64_t srcaddr = 0,
-        uint32_t qos = 0, uint32_t prot = 0, bool error = true) {
+        uint32_t max_bytes = UMI_PACKET_DATA_BYTES, uint32_t qos = 0, uint32_t prot = 0,
+        bool error = true) {
 
         // read "num" bytes from the given address.  "num" may be any value,
         // including greater than the length of a header packet, and values

switchboard/sbdesign.py

@@ -0,0 +1,55 @@
+from siliconcompiler import Design
+from typing import List, Tuple
+
+
+class SbDesign(Design):
+    def __init__(
+            self,
+            name: str = "SbDesign",
+            trace: bool = False,
+            topmodule: str = None,
+            dep: List[Design] = None,
+            files: List[str] = None,
+            idir: List[str] = None,
+            define: List[str] = None,
+            undefine: List[str] = None,
+            param: List[Tuple] = None
+    ):
+
+        super().__init__(name)
+
+        # Taking care of Nones
+        if idir is None:
+            idir = []
+        if dep is None:
+            dep = []
+        if define is None:
+            define = []
+        if undefine is None:
+            undefine = []
+        if param is None:
+            param = []
+
+        # Setting RTL list, others outside
+        with self.active_fileset('rtl'):
+            if topmodule:
+                self.set_topmodule(topmodule)
+            for item in files:
+                self.add_file(item)
+            for item in idir:
+                self.add_idir(item)
+            for item in dep:
+                self.add_depfileset(item)
+            for item in define:
+                self.add_define(item)
+            for item in undefine:
+                self.add_undefine(item)
+            for item in param:
+                self.add_param(item[0], item[1])
+
+        with self.active_fileset('icarus'):
+            if topmodule:
+                self.set_topmodule(topmodule)
+            self.add_depfileset(self, 'rtl')
+            if trace:
+                self.add_define("SB_TRACE")

switchboard/sbdut.py

@@ -246,12 +246,6 @@ def __init__(
             elif self.tool == 'verilator':
                 self._configure_verilator()
 
-            if trace:
-                self.design.add_define("SB_TRACE")
-
-            if self.trace_type == 'fst':
-                self.design.add_define("SB_TRACE_FST")
-
         else:
             from switchboard.sc.standalone_netlist_flow import StandaloneNetlistFlow
             self.set_flow(StandaloneNetlistFlow())