Update clk_divider_tb.v

D3r3k23 · Apr 20, 2021 · 5d343ae · 5d343ae
1 parent 222fbc1
commit 5d343ae
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/clk_divider_tb.v b/clk_divider_tb.v
@@ -12,7 +12,7 @@ module clk_divider_tb;
 
     // 1 kHz clock gen
     initial     clk_in = 1'b0;
-    always #500 clk_in <= ~clk_in; // 1 ms period
+    always #500 clk_in = ~clk_in; // 1 ms period
 
     clk_divider #( .DIV(10) ) DUT // Divide clock frequency by 10
     (