[NOT FOR MERGE] Raptor cs talos 2/patches

.checkpatch.conf

@@ -38,3 +38,4 @@
 --exclude src/vendorcode/cavium
 --exclude src/vendorcode/intel
 --exclude src/vendorcode/mediatek
+--exclude src/vendorcode/ibm

.gitmodules

@@ -1,67 +1,70 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid
 	branch = trunk
+[submodule "3rdparty/sb-signing-utils"]
+	path = 3rdparty/sb-signing-utils
+	url = https://github.com/open-power/sb-signing-utils.git

Documentation/drivers/ipmi_bt.md

@@ -0,0 +1,34 @@
+# IPMI BT driver
+
+The driver can be found in `src/drivers/ipmi/` (same as KCS). It works with BMC
+that provide a BT I/O interface as specified in the [IPMI] standard.
+
+The driver detects the IPMI version and reserves the I/O space in coreboot's
+resource allocator.
+
+## For developers
+
+To use the driver, select the `IPMI_BT` Kconfig and add the following PNP
+device (in example for the BT at 0xe4):
+
+```
+ chip drivers/ipmi
+   device pnp e4.0 on end         # IPMI BT
+ end
+```
+
+**Note:** The I/O base address needs to be aligned to 4.
+
+The following registers can be set:
+
+* `wait_for_bmc`
+  * Boolean
+  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
+    after PoR.
+* `bmc_boot_timeout`
+  * Integer
+  * The timeout in seconds to wait for the IPMI service to be loaded.
+    Will be used if wait_for_bmc is true.
+
+
+[IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/drivers/ipmi_kcs.md

@@ -42,6 +42,15 @@ The following registers can be set:
 * `gpe_interrupt`
   * Integer
   * The bit in GPE (SCI) used to notify about a change on the KCS.
+* `wait_for_bmc`
+  * Boolean
+  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
+    after PoR:
+     - AST2400 on Supermicro X11SSH: 34 s
+* `bmc_boot_timeout`
+  * Integer
+  * The timeout in seconds to wait for the IPMI service to be loaded.
+    Will be used if wait_for_bmc is true.
 
 
 [IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Makefile.inc

@@ -519,7 +519,7 @@ endif
 
 additional-dirs += $(objutil)/cbfstool $(objutil)/ifdtool \
 		   $(objutil)/options $(objutil)/amdfwtool \
-		   $(objutil)/cbootimage
+		   $(objutil)/cbootimage $(objutil)/ffs
 
 export $(COREBOOT_EXPORTS)
 
@@ -561,6 +561,8 @@ IFITTOOL:=$(objutil)/cbfstool/ifittool
 AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress
 CSE_FPT:=$(objutil)/cbfstool/cse_fpt
 CSE_SERGER:=$(objutil)/cbfstool/cse_serger
+ECCTOOL:=$(objutil)/ffs/ecc/ecc
+SBSIGNTOOLS:=$(objutil)/sb-signing-utils/create-container
 
 $(obj)/cbfstool: $(CBFSTOOL)
 	cp $< $@
@@ -601,6 +603,18 @@ IFDTOOL:=$(objutil)/ifdtool/ifdtool
 
 AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
 
+$(ECCTOOL):
+	@printf "    Compile ECCTOOL\n"
+	cp -r $(top)/3rdparty/ffs $(objutil)
+	cd $(objutil)/ffs && autoreconf -i && ./configure
+	+$(MAKE) -C $(objutil)/ffs
+
+$(SBSIGNTOOLS):
+	@printf "    Compile SB SIGNING UTILS\n"
+	cp -r $(top)/3rdparty/sb-signing-utils $(objutil)
+	cd $(objutil)/sb-signing-utils && autoreconf -i -Wno-unsupported && ./configure
+	+$(MAKE) -C $(objutil)/sb-signing-utils
+
 APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
 
 APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py
@@ -701,7 +715,7 @@ install-git-commit-clangfmt:
 include util/crossgcc/Makefile.inc
 
 .PHONY: tools
-tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER)
+tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(ECCTOOL) $(SBSIGNTOOLS)
 
 ###########################################################################
 # Common recipes for all stages
@@ -1146,7 +1160,9 @@ add_intermediate = \
 	$(1): $(obj)/coreboot.pre $(2) | $(INTERMEDIATE) \
 	$(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1))
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(CBFSTOOL) $(IFITTOOL) $$(INTERMEDIATE)
+KEYLOC?=/tmp/keys
+
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(CBFSTOOL) $(IFITTOOL) $(ECCTOOL) $(SBSIGNTOOLS) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 # The full ROM may be larger than the CBFS part, so create an empty
 # file (filled with \377 = 0xff) and copy the CBFS image over it.
@@ -1173,6 +1189,28 @@ ifeq ($(CONFIG_CBFS_VERIFICATION),y)
 		exit 1 ;\
 	fi
 endif # CONFIG_CBFS_VERIFICATION
+ifeq ($(CONFIG_ARCH_PPC64),y)
+	cp -r $(top)/3rdparty/sb-signing-utils/test/keys /tmp
+	@printf "    SBSIGN  $(subst $(obj)/,,$(@))\n"
+	$(SBSIGNTOOLS) -a $(KEYLOC)/hw_key_a.key -b $(KEYLOC)/hw_key_b.key -c $(KEYLOC)/hw_key_c.key \
+	               -p $(KEYLOC)/hw_key_a.key --payload $(top)/$@ --imagefile $(top)/[email protected]
+	@printf "    ECC     $(subst $(obj)/,,$(@))\n"
+	$(ECCTOOL) --inject $(top)/[email protected] --output $(top)/[email protected] --p8
+ifeq ($(CONFIG_BOOTBLOCK_IN_SEEPROM),y)
+	@printf "    ECC     bootblock\n"
+	$(ECCTOOL) --inject $(top)/$(objcbfs)/bootblock.bin --output $(obj)/bootblock.ecc --p8
+else
+	@printf "    SBSIGN  bootblock\n"
+	$(SBSIGNTOOLS) -a $(KEYLOC)/hw_key_a.key -b $(KEYLOC)/hw_key_b.key -c $(KEYLOC)/hw_key_c.key \
+	               -p $(KEYLOC)/hw_key_a.key --payload $(top)/$(objcbfs)/bootblock.bin \
+	               --imagefile $(top)/$(obj)/bootblock.signed
+	$(ECCTOOL) --inject $(top)/$@ --output $(top)/[email protected] --p8
+	@printf "    ECC     bootblock\n"
+	dd  if=$(obj)/bootblock.signed  of=$(obj)/bootblock.signed.pad  ibs=25486 conv=sync 2> /dev/null
+	$(ECCTOOL) --inject $(obj)/bootblock.signed.pad --output $(obj)/bootblock.signed.ecc --p8
+	rm $(obj)/bootblock.signed $(obj)/bootblock.signed.pad
+endif # CONFIG_BOOTBLOCK_IN_SEEPROM
+endif # CONFIG_ARCH_PPC64
 
 cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage
 $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf

configs/config.raptor-cs-talos-2

@@ -0,0 +1,2 @@
+CONFIG_VENDOR_RAPTOR_CS=y
+CONFIG_PAYLOAD_SKIBOOT=y

payloads/external/skiboot/Kconfig

@@ -7,13 +7,15 @@ config PAYLOAD_FILE
 
 config SKIBOOT_GIT_REPO
 	string "Git repository of skiboot payload"
-	default "https://github.com/open-power/skiboot"
+	default "https://github.com/open-power/skiboot" if !BOARD_RAPTOR_CS_TALOS_2
+	default "https://github.com/Dasharo/skiboot.git" if BOARD_RAPTOR_CS_TALOS_2
 	help
 	  Git repository which will be used to clone skiboot.
 
 config SKIBOOT_REVISION
 	string "Revision of skiboot payload"
 	default "d93ddbd39b4eeac0bc11dacbdadea76df2996c13" if BOARD_EMULATION_QEMU_POWER9
+	default "1b14dd0b695b6113805186faad9b2def1d1bfeca" if BOARD_RAPTOR_CS_TALOS_2
 	help
 	  Revision, that skiboot repository will be checked out to, before building
 	  an image.

payloads/external/skiboot/Makefile

@@ -14,7 +14,7 @@ unexport $(COREBOOT_EXPORTS)
 all: $(skiboot_elf)
 
 $(skiboot_elf): | $(skiboot_dir) $(build_dir)
-	+$(MAKE) -C $(skiboot_dir) CROSS="$(skiboot_cross)"
+	+$(MAKE) -C $(skiboot_dir) CROSS="$(skiboot_cross)" skiboot.elf
 	cp $(skiboot_dir)/skiboot.elf $@
 	# skiboot is always built with debug information due to unconditional -ggdb
 	$(skiboot_cross)strip $@
@@ -32,5 +32,6 @@ distclean: clean
 clean:
 	# Redefine RM because it's used like `$(RM) non-existent-file`
 	# Also ignore useless messages about removing test files
-	[ ! -d $(skiboot_dir) ] || $(MAKE) -C $(skiboot_dir) RM="rm -rf" clean > /dev/null
+	[ ! -d $(skiboot_dir) ] || \
+	        $(MAKE) -C $(skiboot_dir) RM="rm -rf" CROSS="$(skiboot_cross)" clean > /dev/null
 	rm -rf $(build_dir)

src/Kconfig

@@ -229,7 +229,7 @@ config INCLUDE_CONFIG_FILE
 
 config COLLECT_TIMESTAMPS
 	bool "Create a table of timestamps collected during boot"
-	default y if ARCH_X86
+	default y if ARCH_X86 || ARCH_PPC64
 	help
 	  Make coreboot create a table of timer-ID/timer-value pairs to
 	  allow measuring time spent at different phases of the boot process.

src/arch/ppc64/Makefile.inc

@@ -1,8 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8
+ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8 -mno-pointers-to-nested-functions
 
-ppc64_asm_flags =
+ppc64_asm_flags = -Wa,--fatal-warnings
 
 ################################################################################
 ## bootblock
@@ -12,7 +12,6 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y)
 bootblock-y = bootblock_crt0.S
 bootblock-y += arch_timer.c
 bootblock-y += boot.c
-bootblock-y += rom_media.c
 bootblock-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \
@@ -38,16 +37,13 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y)
 romstage-y += arch_timer.c
 romstage-y += boot.c
 romstage-y += stages.c
-romstage-y += rom_media.c
 romstage-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \
 	$(top)/src/lib/memcpy.c \
 	$(top)/src/lib/memmove.c \
 	$(top)/src/lib/memset.c
 
-romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-
 # Build the romstage
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
@@ -64,7 +60,7 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y)
 
-ramstage-y += rom_media.c
+ramstage-y += arch_timer.c
 ramstage-y += stages.c
 ramstage-y += arch_timer.c
 ramstage-y += boot.c
@@ -78,8 +74,6 @@ ramstage-y += \
 
 $(eval $(call create_class_compiler,rmodules,power8))
 
-ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 # Build the ramstage