This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock manager (MMCM) for the Xilinx® 7 series FPGA
Useage
1.Move into work
2.Open vivado
3.In the TCL console: source ../scripts/readout_mmcmRC.tcl
4.Generate Bitstream and download it into the KC705 board
5.Make sure your computer connects the board correctly
6.Move into directory software
7.In the terminal:python mmcm_top.py
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EECScat/MMCM_Dynamic-Reconfiguration
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This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock manager (MMCM) for the Xilinx® 7 series FPGA
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