Failed IC's

library/SubcircuitLibrary/ina128/INA128-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# lm_741
+#
+DEF lm_741 X 0 40 Y Y 1 F N
+F0 "X" -200 0 60 H V C CNN
+F1 "lm_741" -100 -250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N
+X off_null 1 -50 400 200 D 50 38 1 1 I
+X inv 2 -550 150 200 R 50 38 1 1 I
+X non_inv 3 -550 -100 200 R 50 38 1 1 I
+X v_neg 4 -150 -450 200 U 50 38 1 1 I
+X off_null 5 50 350 200 D 50 38 1 1 I
+X out 6 550 0 200 L 50 38 1 1 O
+X v_pos 7 -150 450 200 D 50 38 1 1 I
+X strobe 8 50 -350 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library

library/SubcircuitLibrary/ina128/INA128.cir

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+* D:\FOSSEE\eSim\library\SubcircuitLibrary\INA128\INA128.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 08:55:40
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  ? Net-_R6-Pad1_ GND ? ? Net-_R3-Pad1_ ? ? lm_741		
+X3  ? Net-_R8-Pad1_ GND ? ? Net-_R10-Pad1_ ? ? lm_741		
+X2  ? Net-_R3-Pad2_ Net-_R10-Pad2_ ? ? Net-_R4-Pad2_ ? ? lm_741		
+R3  Net-_R3-Pad1_ Net-_R3-Pad2_ 40k		
+R11  Net-_R10-Pad2_ GND 40k		
+R8  Net-_R8-Pad1_ Net-_R10-Pad1_ 25k		
+R6  Net-_R6-Pad1_ Net-_R3-Pad1_ 25k		
+R10  Net-_R10-Pad1_ Net-_R10-Pad2_ 40k		
+R1  Net-_Q1-Pad1_ Net-_R1-Pad2_ 2.2k		
+U2  GND Net-_R1-Pad2_ zener		
+R2  Net-_Q2-Pad2_ Net-_R1-Pad2_ 1k		
+Q2  Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ eSim_PNP		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ GND eSim_PNP		
+R5  GND Net-_Q1-Pad2_ 6.8k		
+R9  Net-_Q3-Pad1_ Net-_R12-Pad2_ 2.2k		
+U3  GND Net-_R12-Pad2_ zener		
+R12  Net-_Q4-Pad2_ Net-_R12-Pad2_ 1k		
+Q4  Net-_Q3-Pad1_ Net-_Q4-Pad2_ Net-_Q3-Pad2_ eSim_PNP		
+Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ GND eSim_PNP		
+R13  GND Net-_Q3-Pad2_ 6.8k		
+R4  Net-_R3-Pad2_ Net-_R4-Pad2_ 40k		
+U1  ? Net-_Q1-Pad1_ Net-_R4-Pad2_ Net-_R6-Pad1_ Net-_Q3-Pad1_ Net-_R8-Pad1_ GND ? PORT		
+R7  Net-_R4-Pad2_ GND 10k		
+
+.end

library/SubcircuitLibrary/ina128/INA128.cir.out

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+* d:\fossee\esim\library\subcircuitlibrary\ina128\ina128.cir
+
+.include lm_741.sub
+.include PNP.lib
+x1 ? net-_r6-pad1_ gnd ? ? net-_r3-pad1_ ? ? lm_741
+x3 ? net-_r8-pad1_ gnd ? ? net-_r10-pad1_ ? ? lm_741
+x2 ? net-_r3-pad2_ net-_r10-pad2_ ? ? net-_r4-pad2_ ? ? lm_741
+r3  net-_r3-pad1_ net-_r3-pad2_ 40k
+r11  net-_r10-pad2_ gnd 40k
+r8  net-_r8-pad1_ net-_r10-pad1_ 25k
+r6  net-_r6-pad1_ net-_r3-pad1_ 25k
+r10  net-_r10-pad1_ net-_r10-pad2_ 40k
+r1  net-_q1-pad1_ net-_r1-pad2_ 2.2k
+* u2  gnd net-_r1-pad2_ zener
+r2  net-_q2-pad2_ net-_r1-pad2_ 1k
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q1-pad2_ Q2N2907A
+q1 net-_q1-pad1_ net-_q1-pad2_ gnd Q2N2907A
+r5  gnd net-_q1-pad2_ 6.8k
+r9  net-_q3-pad1_ net-_r12-pad2_ 2.2k
+* u3  gnd net-_r12-pad2_ zener
+r12  net-_q4-pad2_ net-_r12-pad2_ 1k
+q4 net-_q3-pad1_ net-_q4-pad2_ net-_q3-pad2_ Q2N2907A
+q3 net-_q3-pad1_ net-_q3-pad2_ gnd Q2N2907A
+r13  gnd net-_q3-pad2_ 6.8k
+r4  net-_r3-pad2_ net-_r4-pad2_ 40k
+* u1  ? net-_q1-pad1_ net-_r4-pad2_ net-_r6-pad1_ net-_q3-pad1_ net-_r8-pad1_ gnd ? port
+r7  net-_r4-pad2_ gnd 10k
+a1 gnd net-_r1-pad2_ u2
+a2 gnd net-_r12-pad2_ u3
+* Schematic Name:                             zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) 
+* Schematic Name:                             zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

library/SubcircuitLibrary/ina128/INA128.pro

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+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts