feat: Add support for x86_64 backend #476
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…pport As part of the x86_64 backend development (PR JonasKruckenberg#476), this commit refactors trap handling to be architecture-independent: - Create dedicated 'trap' library at libs/trap/ for architecture-independent trap types - Move Trap, Interrupt, and Exception enums from RISC-V-specific code to shared library - Update RISC-V library to import trap types from the new shared library - Update kernel trap_handler to use the generic trap interface - Add trap library to workspace dependencies This refactoring enables code sharing between RISC-V and future x86_64 implementations, eliminating duplication and creating a clean architecture-agnostic interface for trap handling. Verified: RISC-V kernel boots and runs successfully with these changes. Related to: JonasKruckenberg#476 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude <[email protected]>
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Heya! Exciting work you're doing here, really looking forward to landing it! Let me know what I can help with to make this possible! Just one comment about AI (bc we don't have an AI policy statement just yet): TLDR; You're reponsible for the code you commit regardless of tooling choice. I personally have mixed feelings about AI but have no problem with you using it (in fact if we want to get a real OS going we'll need all the help we can get). This was probably obvious to you already, just a heads up :) |
Co-authored-by: Jonas Kruckenberg <[email protected]>
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* refactor: create generic trap interface library for x86_64 backend support As part of the x86_64 backend development (PR #476), this commit refactors trap handling to be architecture-independent: - Create dedicated 'trap' library at libs/trap/ for architecture-independent trap types - Move Trap, Interrupt, and Exception enums from RISC-V-specific code to shared library - Update RISC-V library to import trap types from the new shared library - Update kernel trap_handler to use the generic trap interface - Add trap library to workspace dependencies This refactoring enables code sharing between RISC-V and future x86_64 implementations, eliminating duplication and creating a clean architecture-agnostic interface for trap handling. Verified: RISC-V kernel boots and runs successfully with these changes. Related to: #476 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude <[email protected]> * fmt * Update libs/trap/Cargo.toml Co-authored-by: Jonas Kruckenberg <[email protected]> * rm RISCV specific enum tags * mv rv trap defs back to scause.rs * properly define and impl arch::trap::Trap * fmt --------- Co-authored-by: Claude <[email protected]> Co-authored-by: Jonas Kruckenberg <[email protected]>
1. kernel/src/arch/x86_64/mod.rs:
- Fixed FS_BASE MSR: Changed TLS base from 0xffffffc080000000 to 0xffffffc080001000
- Removed panic in per_cpu_init_late() to allow boot to continue
2. kernel/src/arch/x86_64/mem.rs:
- Fixed KERNEL_ASPACE_RANGE: Changed from 0xffff800000000000 to 0xffffffc000000000
- Implemented AddressSpace::from_active(): Now reads actual CR3 register instead of using 0
3. kernel/src/arch/x86_64/trap_handler.rs:
- Removed panic in init(), allowing boot without IDT setup
4. kernel/src/arch/x86_64/entry.s (new file):
- Added assembly entry point to properly handle x86_64 calling convention
5. kernel/src/main.rs:
- Added x86_64-specific entry point handling
- Added debug prints to trace boot progress (these are temporary)
- Added FDT magic number checking for x86_64
6. Other files: Minor debug additions and x86_64 compatibility fixes
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