Skip to content
View KapoorAkshit18's full-sized avatar
👨‍🦱
I may be slow to respond.
👨‍🦱
I may be slow to respond.
  • Shri Mata Vaishno Devi University (SMVDU), Katra

Block or report KapoorAkshit18

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. RTL_Code_Verilog RTL_Code_Verilog Public

    Basic building block of the digital circuit is written in verilog like half adder. full adder, multiplexer,flipflops of various configurations, and other synchrounous circuits

  2. nasscom-vsd-soc-design-workshop nasscom-vsd-soc-design-workshop Public