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refactor: interrupt
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Signed-off-by: Zone.N <[email protected]>
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@MRNIU
MRNIU committed Feb 8, 2025
1 parent 82cfaa3 commit 0e1080c
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Showing 2 changed files with 68 additions and 68 deletions.
38 changes: 19 additions & 19 deletions src/kernel/driver/gic/gic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -125,44 +125,44 @@ Gic::Gicr::Gicr(uint64_t base_addr) : base_addr_(base_addr) {

auto cpuid = cpu_io::GetCurrentCoreId();

Write(cpuid, kGICR_CTLR, 0);
Write(cpuid, kCTLR, 0);

cpu_io::ICC_SRE_EL1::SRE::Set();

Write(cpuid, kGICR_IGROUPR0, ~0);
Write(cpuid, kGICR_IGRPMODR0, 0);
Write(cpuid, kIGROUPR0, ~0);
Write(cpuid, kIGRPMODR0, 0);

uint32_t waker = Read(cpuid, kGICR_WAKER);
Write(cpuid, kGICR_WAKER, waker & ~(1 << 1));
while (Read(cpuid, kGICR_WAKER) & (1 << 2)) {
uint32_t waker = Read(cpuid, kWAKER);
Write(cpuid, kWAKER, waker & ~(1 << 1));
while (Read(cpuid, kWAKER) & (1 << 2)) {
;
}
}

void Gic::Gicr::Enable(uint32_t intid, uint32_t cpuid) const {
auto is = Read(cpuid, kGICR_ISENABLER0);
is |= 1 << (intid % kGICR_ISENABLER0_SIZE);
Write(cpuid, kGICR_ISENABLER0, is);
auto is = Read(cpuid, kISENABLER0);
is |= 1 << (intid % kISENABLER0_SIZE);
Write(cpuid, kISENABLER0, is);
}

void Gic::Gicr::Disable(uint32_t intid, uint32_t cpuid) const {
auto ic = Read(cpuid, kGICR_ICENABLER0);
ic |= 1 << (intid % kGICR_ICENABLER0_SIZE);
Write(cpuid, kGICR_ICENABLER0, ic);
auto ic = Read(cpuid, kICENABLER0);
ic |= 1 << (intid % kICENABLER0_SIZE);
Write(cpuid, kICENABLER0, ic);
}

void Gic::Gicr::Clear(uint32_t intid, uint32_t cpuid) const {
auto ic = Read(cpuid, kGICR_ICPENDR0);
ic |= 1 << (intid % kGICR_ICPENDR0_SIZE);
Write(cpuid, kGICR_ICPENDR0, ic);
auto ic = Read(cpuid, kICPENDR0);
ic |= 1 << (intid % kICPENDR0_SIZE);
Write(cpuid, kICPENDR0, ic);
}

void Gic::Gicr::SetPrio(uint32_t intid, uint32_t cpuid, uint32_t prio) const {
auto shift = (intid % kGICR_IPRIORITYRn_SIZE) * kGICR_IPRIORITYRn_BITS;
auto ip = Read(cpuid, GICR_IPRIORITYRn(intid / kGICR_IPRIORITYRn_SIZE));
ip &= ~(kGICR_IPRIORITYRn_BITS_MASK << shift);
auto shift = (intid % kIPRIORITYRn_SIZE) * kIPRIORITYRn_BITS;
auto ip = Read(cpuid, IPRIORITYRn(intid / kIPRIORITYRn_SIZE));
ip &= ~(kIPRIORITYRn_BITS_MASK << shift);
ip |= prio << shift;
Write(cpuid, GICR_IPRIORITYRn(intid / kGICR_IPRIORITYRn_SIZE), ip);
Write(cpuid, IPRIORITYRn(intid / kIPRIORITYRn_SIZE), ip);
}

void Gic::Gicr::SetupPPI(uint32_t intid, uint32_t cpuid) const {
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98 changes: 49 additions & 49 deletions src/kernel/driver/gic/include/gic.h
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Original file line number Diff line number Diff line change
Expand Up @@ -368,107 +368,107 @@ class Gic {
class Gicr {
public:
/// 每个 GICR 长度 2 * 64 * 1024
static constexpr const uint32_t kGICR_STRIDE = 0x20000;
static constexpr const uint32_t kSTRIDE = 0x20000;
/// Redistributor Control Register, RW
static constexpr const uint32_t kGICR_CTLR = 0x0000;
static constexpr const uint32_t kCTLR = 0x0000;
/// Redistributor Implementation Identification Register, RO
static constexpr const uint32_t kGICR_IIDR = 0x0004;
static constexpr const uint32_t kIIDR = 0x0004;
/// Redistributor Type Register, RO
static constexpr const uint32_t kGICR_TYPER = 0x0008;
static constexpr const uint32_t kTYPER = 0x0008;
/// Power Management Control Register, RW1
static constexpr const uint32_t kGICR_WAKER = 0x0014;
static constexpr const uint32_t kWAKER = 0x0014;
/// Function Control Register, RW
static constexpr const uint32_t kGICR_FCTLR = 0x0020;
static constexpr const uint32_t kFCTLR = 0x0020;
/// Power Register, RW
static constexpr const uint32_t kGICR_PWRR = 0x0024;
static constexpr const uint32_t kPWRR = 0x0024;
/// Class Register, RW
static constexpr const uint32_t kGICR_CLASSR = 0x0028;
static constexpr const uint32_t kCLASSR = 0x0028;
/// Redistributor Properties Base Address Register, RW
static constexpr const uint32_t kGICR_PROPBASER = 0x0070;
static constexpr const uint32_t kPROPBASER = 0x0070;
/// Redistributor LPI Pending Table Base Address Register, RW
static constexpr const uint32_t kGICR_PENDBASER = 0x0078;
static constexpr const uint32_t kPENDBASER = 0x0078;
/// Peripheral ID 4 Register, RO
static constexpr const uint32_t kGICR_PIDR4 = 0xFFD0;
static constexpr const uint32_t kPIDR4 = 0xFFD0;
/// Peripheral ID 5 Register, RO
static constexpr const uint32_t kGICR_PIDR5 = 0xFFD4;
static constexpr const uint32_t kPIDR5 = 0xFFD4;
/// Peripheral ID 6 Register, RO
static constexpr const uint32_t kGICR_PIDR6 = 0xFFD8;
static constexpr const uint32_t kPIDR6 = 0xFFD8;
/// Peripheral ID 7 Register, RO
static constexpr const uint32_t kGICR_PIDR7 = 0xFFDC;
static constexpr const uint32_t kPIDR7 = 0xFFDC;
/// Peripheral ID 0 Register, RO
static constexpr const uint32_t kGICR_PIDR0 = 0xFFE0;
static constexpr const uint32_t kPIDR0 = 0xFFE0;
/// Peripheral ID 1 Register, RO
static constexpr const uint32_t kGICR_PIDR1 = 0xFFE4;
static constexpr const uint32_t kPIDR1 = 0xFFE4;
/// Peripheral ID 2 Register, RO
static constexpr const uint32_t kGICR_PIDR2 = 0xFFE8;
static constexpr const uint32_t kPIDR2 = 0xFFE8;
/// Peripheral ID 3 Register, RO
static constexpr const uint32_t kGICR_PIDR3 = 0xFFEC;
static constexpr const uint32_t kPIDR3 = 0xFFEC;
/// Component ID 0 Register, RO
static constexpr const uint32_t kGICR_CIDR0 = 0xFFF0;
static constexpr const uint32_t kCIDR0 = 0xFFF0;
/// Component ID 1 Register, RO
static constexpr const uint32_t kGICR_CIDR1 = 0xFFF4;
static constexpr const uint32_t kCIDR1 = 0xFFF4;
/// Component ID 2 Register, RO
static constexpr const uint32_t kGICR_CIDR2 = 0xFFF8;
static constexpr const uint32_t kCIDR2 = 0xFFF8;
/// Component ID 3 Register, RO
static constexpr const uint32_t kGICR_CIDR3 = 0xFFFC;
static constexpr const uint32_t kCIDR3 = 0xFFFC;

/// SGI 基地址 64 * 1024
static constexpr const uint32_t kGICR_SGI_BASE = 0x10000;
static constexpr const uint32_t kSGI_BASE = 0x10000;
/// Interrupt Group Register, RW
static constexpr const uint32_t kGICR_IGROUPR0 = kGICR_SGI_BASE + 0x0080;
static constexpr const uint32_t kIGROUPR0 = kSGI_BASE + 0x0080;

/// Interrupt Set-Enable Register, RW
/// @see
/// https://developer.arm.com/documentation/ddi0601/2024-12/External-Registers/GICR-ISENABLER0--Interrupt-Set-Enable-Register-0?lang=en
static constexpr const uint32_t kGICR_ISENABLER0 = kGICR_SGI_BASE + 0x0100;
static constexpr const uint32_t kGICR_ISENABLER0_SIZE = 32;
static constexpr const uint32_t kISENABLER0 = kSGI_BASE + 0x0100;
static constexpr const uint32_t kISENABLER0_SIZE = 32;

/// Interrupt Clear-Enable Register, RW
/// @see
/// https://developer.arm.com/documentation/ddi0601/2024-12/External-Registers/GICR-ICENABLER0--Interrupt-Clear-Enable-Register-0?lang=en
static constexpr const uint32_t kGICR_ICENABLER0 = kGICR_SGI_BASE + 0x0180;
static constexpr const uint32_t kGICR_ICENABLER0_SIZE = 32;
static constexpr const uint32_t kICENABLER0 = kSGI_BASE + 0x0180;
static constexpr const uint32_t kICENABLER0_SIZE = 32;

/// Interrupt Set-Pending Register, RW
static constexpr const uint32_t kGICR_ISPENDR0 = kGICR_SGI_BASE + 0x0200;
static constexpr const uint32_t kISPENDR0 = kSGI_BASE + 0x0200;

/// Peripheral Clear Pending Register, RW
/// @see
/// https://developer.arm.com/documentation/ddi0601/2024-12/External-Registers/GICR-ICPENDR0--Interrupt-Clear-Pending-Register-0?lang=en
static constexpr const uint32_t kGICR_ICPENDR0 = kGICR_SGI_BASE + 0x0280;
static constexpr const uint32_t kGICR_ICPENDR0_SIZE = 32;
static constexpr const uint32_t kICPENDR0 = kSGI_BASE + 0x0280;
static constexpr const uint32_t kICPENDR0_SIZE = 32;

/// Interrupt Set-Active Register, RW
static constexpr const uint32_t kGICR_ISACTIVER0 = kGICR_SGI_BASE + 0x0300;
static constexpr const uint32_t kISACTIVER0 = kSGI_BASE + 0x0300;
/// Interrupt Clear-Active Register, RW
static constexpr const uint32_t kGICR_ICACTIVER0 = kGICR_SGI_BASE + 0x0380;
static constexpr const uint32_t kICACTIVER0 = kSGI_BASE + 0x0380;
/// Interrupt Priority Registers, RW
/// @see
/// https://developer.arm.com/documentation/ddi0601/2024-12/External-Registers/GICR-IPRIORITYR-n---Interrupt-Priority-Registers?lang=en
static constexpr const uint32_t kGICR_IPRIORITYRn = kGICR_SGI_BASE + 0x0400;
static constexpr const uint32_t kGICR_IPRIORITYRn_SIZE = 4;
static constexpr const uint32_t kGICR_IPRIORITYRn_BITS = 8;
static constexpr const uint32_t kGICR_IPRIORITYRn_BITS_MASK = 0xFF;
__always_inline auto GICR_IPRIORITYRn(uint64_t n) const -> uint64_t {
return kGICR_IPRIORITYRn + n * 4;
static constexpr const uint32_t kIPRIORITYRn = kSGI_BASE + 0x0400;
static constexpr const uint32_t kIPRIORITYRn_SIZE = 4;
static constexpr const uint32_t kIPRIORITYRn_BITS = 8;
static constexpr const uint32_t kIPRIORITYRn_BITS_MASK = 0xFF;
__always_inline auto IPRIORITYRn(uint64_t n) const -> uint64_t {
return kIPRIORITYRn + n * 4;
}

/// Interrupt Configuration Registers, RW
static constexpr const uint32_t kGICR_ICFGRn = 0x0C00;
static constexpr const uint32_t kICFGRn = 0x0C00;
/// Interrupt Group Modifier Register, RW
static constexpr const uint32_t kGICR_IGRPMODR0 = 0x0D00;
static constexpr const uint32_t kIGRPMODR0 = 0x0D00;
/// Non-secure Access Control Register, RW
static constexpr const uint32_t kGICR_NSACR = 0x0E00;
static constexpr const uint32_t kNSACR = 0x0E00;
/// Miscellaneous Status Register, RO
static constexpr const uint32_t kGICR_MISCSTATUSR = 0xC000;
static constexpr const uint32_t kMISCSTATUSR = 0xC000;
/// Interrupt Error Valid Register, RW
static constexpr const uint32_t kGICR_IERRVR = 0xC008;
static constexpr const uint32_t kIERRVR = 0xC008;
/// SGI Default Register, RW
static constexpr const uint32_t kGICR_SGIDR = 0xC010;
static constexpr const uint32_t kSGIDR = 0xC010;
/// Configuration ID0 Register, RO
static constexpr const uint32_t kGICR_CFGID0 = 0xF000;
static constexpr const uint32_t kCFGID0 = 0xF000;
/// Configuration ID1 Register, RO
static constexpr const uint32_t kGICR_CFGID1 = 0xF004;
static constexpr const uint32_t kCFGID1 = 0xF004;

/**
* 构造函数
Expand Down Expand Up @@ -528,12 +528,12 @@ class Gic {
uint64_t base_addr_ = 0;

__always_inline auto Read(uint32_t cpuid, uint32_t off) const -> uint32_t {
return io::In<uint32_t>(base_addr_ + cpuid * kGICR_STRIDE + off);
return io::In<uint32_t>(base_addr_ + cpuid * kSTRIDE + off);
}

__always_inline void Write(uint32_t cpuid, uint32_t off,
uint32_t val) const {
io::Out<uint32_t>(base_addr_ + cpuid * kGICR_STRIDE + off, val);
io::Out<uint32_t>(base_addr_ + cpuid * kSTRIDE + off, val);
}
};

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