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axis_uart_bridge

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

generic

Name	Type	Range	Description
UART_SPEED	integer	> 0	Speed in baud/s
FREQ_HZ	integer	> (UART_SPEED*4)	clock frequency in hz
N_BYTES	integer	> 0	data width in bytes
QUEUE_DEPTH	integer	>= 0	internal queue depth, if 0 - no queue
QUEUE_MEMTYPE	string	"auto", "block", "distributed", "ultra"	type of internal queue, if QUEUE_DEPTH = 0 then ignored
UART_TX_REGISTER_LEN	integer	>= 0	length of flip-flop cascade for UART_TX signal from logic to PAD
UART_RX_REGISTER_LEN	integer	>= 0	length of flip-flop cascade for UART_RX signal from PAD to logic

Ports

Control

Name	Direction	width	Description
aclk	input	1	CLK signal
aresetn	input	1	reset signal, low-level active

AXI-Stream

Slave AXI-Stream

Name	Direction	Width	Description
S_AXIS_TDATA	input	N_BYTES*8	bus for send data from logic to external UART device
S_AXIS_TVALID	input	1	data valid signal
S_AXIS_TREADY	output	1	data ready signal

Master AXI-Stream

Name	Direction	Width	Description
M_AXIS_TDATA	output	N_BYTES*8	data bus for receive data from external UART device to logic
M_AXIS_TVALID	output	1	data valid signal
M_AXIS_TREADY	input	1	data ready signal

Component description

• component consists of two independent modules:

1. axis_uart_bridge_rx - for receive from UART and transmit to AXI-Stream bus
2. axis_uart_bridge_tx - for receive from AXI-Stream and transmit to UART

• only common clock support, independent clocks unsupported

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axis_uart_bridge_tx

Component for receiving data from UART interface and transmit to AXI-Stream

1. START byte
2. 8 bit data
3. STOP byte

Component not supports TKEEP for AXI-Stream. All Word was fully transitted. Packet boundary, or TLAST signal doesnt support for this implementation

UART byte duration calculated as : CLOCK_DURATION = FREQ_HZ/UART_SPEED

FREQ_HZ must be greater than UART_SPEED for 4 times.

Component work according Finite State Machine(fsm). State diagram presented in table

Current state	Next state	Condition	State description
IDLE_ST	START_ST	Input queue isnt empty	wait for new word on AXI-Stream for transmission
START_ST	DATA_ST	event for finalize transmit START byte	START byte transmission state
DATA_ST	STOP_ST	finalize for symbol transmit and bit counter equal 7	Data transmit state. In this state transmit only one byte of data
STOP_ST	START_ST	1. Finalize for symbol transmit, and number of bytes less than number of bytes in word 2. Finalize transmit byte and input queue isnt empty	STOP byte transmission state