[JitDiff X64] [tannergooding] Ensure other types of SIMD related loads, stor ...

[MihuBot]

Job completed in 20 minutes 54 seconds (remote runner delay: 1 minute 12 seconds).
dotnet/runtime#129563
Using arguments: -nuget -jitutils-repo EgorBo/jitutils -jitutils-branch pmi-deterministic-cctors
Main commit: dotnet/runtime@5a200b4
PR commit: tannergooding/runtime@1af70f3

Diffs

Found 104 files with textual diffs.

Summary of Code Size diffs:
(Lower is better)

Total bytes of base: 341900018
Total bytes of diff: 341899901
Total bytes of delta: -117 (-0.00 % of base)
Total relative delta: -0.41
    diff is an improvement.
    relative diff is an improvement.


Top file improvements (bytes):
        -100 : BepuPhysics.dasm (-0.01 % of base)
         -17 : SixLabors.ImageSharp.dasm (-0.00 % of base)

2 total files with Code Size differences (2 improved, 0 regressed), 689 unchanged.

Top method regressions (bytes):
          15 (0.17 % of base) : BepuPhysics.dasm - BepuPhysics.CollisionDetection.CollisionTasks.CylinderConvexHullTester:Test(byref,byref,byref,byref,byref,byref,int,byref) (FullOpts)
           5 (0.07 % of base) : BepuPhysics.dasm - BepuPhysics.CollisionDetection.CollisionTasks.ConvexHullPairTester:Test(byref,byref,byref,byref,byref,byref,int,byref) (FullOpts)
           2 (0.02 % of base) : BepuPhysics.dasm - BepuPhysics.CollisionDetection.CollisionTasks.BoxConvexHullTester:Test(byref,byref,byref,byref,byref,byref,int,byref) (FullOpts)
           1 (0.51 % of base) : SixLabors.ImageSharp.dasm - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToString():System.String:this (FullOpts)

Top method improvements (bytes):
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[byte](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[double](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[int](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[long](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[short](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[System.Numerics.Vector`1[float]](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
          -9 (-17.65 % of base) : SixLabors.ImageSharp.dasm - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector2():System.Numerics.Vector2:this (FullOpts)
          -9 (-11.39 % of base) : SixLabors.ImageSharp.dasm - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector4():System.Numerics.Vector4:this (FullOpts)
          -2 (-0.48 % of base) : BepuPhysics.dasm - BepuPhysics.Collidables.ConvexHullWide:RayTest(byref,byref,byref,byref,byref):this (FullOpts)

Top method regressions (percentages):
           1 (0.51 % of base) : SixLabors.ImageSharp.dasm - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToString():System.String:this (FullOpts)
          15 (0.17 % of base) : BepuPhysics.dasm - BepuPhysics.CollisionDetection.CollisionTasks.CylinderConvexHullTester:Test(byref,byref,byref,byref,byref,byref,int,byref) (FullOpts)
           5 (0.07 % of base) : BepuPhysics.dasm - BepuPhysics.CollisionDetection.CollisionTasks.ConvexHullPairTester:Test(byref,byref,byref,byref,byref,byref,int,byref) (FullOpts)
           2 (0.02 % of base) : BepuPhysics.dasm - BepuPhysics.CollisionDetection.CollisionTasks.BoxConvexHullTester:Test(byref,byref,byref,byref,byref,byref,int,byref) (FullOpts)

Top method improvements (percentages):
          -9 (-17.65 % of base) : SixLabors.ImageSharp.dasm - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector2():System.Numerics.Vector2:this (FullOpts)
          -9 (-11.39 % of base) : SixLabors.ImageSharp.dasm - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector4():System.Numerics.Vector4:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[byte](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[double](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[int](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[long](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[short](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
         -20 (-2.07 % of base) : BepuPhysics.dasm - BepuPhysics.Trees.Tree:Add[System.Numerics.Vector`1[float]](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
          -2 (-0.48 % of base) : BepuPhysics.dasm - BepuPhysics.Collidables.ConvexHullWide:RayTest(byref,byref,byref,byref,byref):this (FullOpts)

13 total methods with Code Size differences (9 improved, 4 regressed), 1838542 unchanged.

--------------------------------------------------------------------------------

Artifacts:

• jit-diffs-pr.zip (1.0 GB)
• jit-diffs-main.zip (1.0 GB)
• diff-frameworks.txt (5 KB)
• ShortDiffsRegressions.md (9 KB)
• LongDiffsRegressions.md (495 KB)
• ShortDiffsImprovements.md (54 KB)
• LongDiffsImprovements.md (217 KB)

[MihuBot]

Top method regressions

1 (0.51 % of base) - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToString():System.String:this

 ; Assembly listing for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToString():System.String:this (FullOpts)
 ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
 ; FullOpts code
 ; optimized code
 ; rsp based frame
 ; fully interruptible
 ; No PGO data
 ; 0 inlinees with PGO data; 17 single block inlinees; 5 inlinees without PGO data
 ; Final local variable assignments
 ;
 ;  V00 this         [V00,T01] (  4,  4   )   byref  ->  rdi         this single-def
-;* V01 loc0         [V01    ] (  0,  0   )   simd8  ->  zero-ref    single-def <System.Numerics.Vector2>
+;  V01 loc0         [V01,T09] (  3,  3   )   simd8  ->  [rsp+0x00]  spill-single-def <System.Numerics.Vector2>
 ;# V02 OutArgs      [V02    ] (  1,  1   )  struct ( 0) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
 ;  V03 tmp1         [V03,T00] (  4,  8   )     ref  ->  rbx         class-hnd exact single-def "NewArr temp" <System.Object[]>
 ;  V04 tmp2         [V04,T02] (  3,  6   )     ref  ->  rax         class-hnd exact single-def "Single-def Box Helper" <System.Single>
 ;  V05 tmp3         [V05,T03] (  3,  6   )     ref  ->  rax         class-hnd exact single-def "Single-def Box Helper" <System.Single>
-;  V06 tmp4         [V06    ] (  4,  4   )   simd8  ->  [rsp+0x00]  do-not-enreg[SB] must-init ld-addr-op "Inline ldloca(s) first use temp" <System.Numerics.Vector2>
+;  V06 tmp4         [V06,T10] (  2,  2   )   simd8  ->  mm0         ld-addr-op single-def "Inline ldloca(s) first use temp" <System.Numerics.Vector2>
 ;* V07 tmp5         [V07    ] (  0,  0   )  ushort  ->  zero-ref    "Inlining Arg"
 ;* V08 tmp6         [V08    ] (  0,  0   )  struct ( 8) zero-ref    "System.Half tmp" <System.Half>
 ;* V09 tmp7         [V09    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <System.Half>
 ;* V10 tmp8         [V10    ] (  0,  0   )  ushort  ->  zero-ref    "Inlining Arg"
 ;* V11 tmp9         [V11    ] (  0,  0   )  struct ( 8) zero-ref    "System.Half tmp" <System.Half>
 ;* V12 tmp10        [V12    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <System.Half>
 ;* V13 tmp11        [V13    ] (  0,  0   )    long  ->  zero-ref    class-hnd exact "NewObj constructor temp" <System.Runtime.CompilerServices.FormattableStringFactory+ConcreteFormattableString>
 ;* V14 tmp12        [V14    ] (  0,  0   )     ref  ->  zero-ref    class-hnd exact "Inlining Arg" <System.Globalization.CultureInfo>
 ;* V15 tmp13        [V15    ] (  0,  0   )     ref  ->  zero-ref    class-hnd single-def "Inlining Arg" <System.Object[]>
 ;* V16 tmp14        [V16    ] (  0,  0   )     ref  ->  zero-ref    class-hnd exact "Inlining Arg" <System.Globalization.CultureInfo>
 ;* V17 tmp15        [V17    ] (  0,  0   )     ref  ->  zero-ref    class-hnd exact single-def "Inlining Arg" <System.String>
 ;* V18 tmp16        [V18    ] (  0,  0   )  struct (16) zero-ref    "spilled call-like call argument" <System.ReadOnlySpan`1[System.Object]>
 ;* V19 tmp17        [V19    ] (  0,  0   )     ref  ->  zero-ref   
 ;* V20 tmp18        [V20    ] (  0,  0   )  struct (16) zero-ref    multireg-arg ld-addr-op "NewObj constructor temp" <System.ReadOnlySpan`1[System.Object]>
 ;* V21 tmp19        [V21    ] (  0,  0   )  struct (24) zero-ref    do-not-enreg[SF] "stack allocated System.Runtime.CompilerServices.FormattableStringFactory+ConcreteFormattableString" <System.Runtime.CompilerServices.FormattableStringFactory+ConcreteFormattableString>
-;  V22 tmp20        [V22,T09] (  3,  3   )   float  ->  [rsp+0x00]  do-not-enreg[] "field V06.X (fldOffset=0x0)" P-DEP
-;  V23 tmp21        [V23,T10] (  3,  3   )   float  ->  [rsp+0x04]  do-not-enreg[] "field V06.Y (fldOffset=0x4)" P-DEP
-;* V24 tmp22        [V24    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V08._value (fldOffset=0x0)" P-INDEP
-;  V25 tmp23        [V25,T06] (  2,  2   )  ushort  ->  rsi         single-def "field V09._value (fldOffset=0x0)" P-INDEP
-;* V26 tmp24        [V26    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V11._value (fldOffset=0x0)" P-INDEP
-;  V27 tmp25        [V27,T07] (  2,  2   )  ushort  ->  rdi         single-def "field V12._value (fldOffset=0x0)" P-INDEP
-;* V28 tmp26        [V28    ] (  0,  0   )   byref  ->  zero-ref    "field V18._reference (fldOffset=0x0)" P-INDEP
-;* V29 tmp27        [V29    ] (  0,  0   )     int  ->  zero-ref    "field V18._length (fldOffset=0x8)" P-INDEP
-;  V30 tmp28        [V30,T05] (  2,  2   )   byref  ->  rdx         single-def "field V20._reference (fldOffset=0x0)" P-INDEP
-;* V31 tmp29        [V31,T08] (  0,  0   )     int  ->  zero-ref    single-def "field V20._length (fldOffset=0x8)" P-INDEP
-;* V32 tmp30        [V32    ] (  0,  0   )    long  ->  zero-ref    single-def "V21.[000..008)"
-;* V33 tmp31        [V33    ] (  0,  0   )     ref  ->  zero-ref    single-def "V21.[008..016)"
-;* V34 tmp32        [V34    ] (  0,  0   )     ref  ->  zero-ref    single-def "V21.[016..024)"
-;  V35 cse0         [V35,T04] (  3,  3   )    long  ->  r15         "CSE #01: aggressive"
+;* V22 tmp20        [V22    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V08._value (fldOffset=0x0)" P-INDEP
+;  V23 tmp21        [V23,T06] (  2,  2   )  ushort  ->  rsi         single-def "field V09._value (fldOffset=0x0)" P-INDEP
+;* V24 tmp22        [V24    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V11._value (fldOffset=0x0)" P-INDEP
+;  V25 tmp23        [V25,T07] (  2,  2   )  ushort  ->  rdi         single-def "field V12._value (fldOffset=0x0)" P-INDEP
+;* V26 tmp24        [V26    ] (  0,  0   )   byref  ->  zero-ref    "field V18._reference (fldOffset=0x0)" P-INDEP
+;* V27 tmp25        [V27    ] (  0,  0   )     int  ->  zero-ref    "field V18._length (fldOffset=0x8)" P-INDEP
+;  V28 tmp26        [V28,T05] (  2,  2   )   byref  ->  rdx         single-def "field V20._reference (fldOffset=0x0)" P-INDEP
+;* V29 tmp27        [V29,T08] (  0,  0   )     int  ->  zero-ref    single-def "field V20._length (fldOffset=0x8)" P-INDEP
+;* V30 tmp28        [V30    ] (  0,  0   )    long  ->  zero-ref    single-def "V21.[000..008)"
+;* V31 tmp29        [V31    ] (  0,  0   )     ref  ->  zero-ref    single-def "V21.[008..016)"
+;* V32 tmp30        [V32    ] (  0,  0   )     ref  ->  zero-ref    single-def "V21.[016..024)"
+;  V33 cse0         [V33,T04] (  3,  3   )    long  ->  r15         "CSE #01: aggressive"
 ;
 ; Lcl frame size = 8
 
 G_M19285_IG01:
        push     r15
        push     rbx
        push     rax
-       xor      eax, eax
-       mov      qword ptr [rsp], rax
-						;; size=10 bbWeight=1 PerfScore 4.25
+						;; size=4 bbWeight=1 PerfScore 3.00
 G_M19285_IG02:
        movzx    rsi, word  ptr [rdi]
        vmovd    xmm0, esi
        vcvtph2ps xmm0, xmm0
-       vmovss   dword ptr [rsp], xmm0
+       vinsertps xmm0, xmm0, xmm0, 14
        mov      edi, dword ptr [rdi]
        shr      edi, 16
        movzx    rdi, di
-       vmovd    xmm0, edi
-       vcvtph2ps xmm0, xmm0
-       vmovss   dword ptr [rsp+0x04], xmm0
+       vmovd    xmm1, edi
+       vcvtph2ps xmm1, xmm1
+       vinsertps xmm0, xmm0, xmm1, 16
+       vmovsd   qword ptr [rsp], xmm0
        mov      rdi, 0xD1FFAB1E      ; System.Object[]
        mov      esi, 2
        call     CORINFO_HELP_NEWARR_1_PTR
        mov      rbx, rax
        mov      r15, 0xD1FFAB1E      ; System.Single
        mov      rdi, r15
        call     CORINFO_HELP_NEWSFAST
-       vmovss   xmm0, dword ptr [rsp]
+       vmovsd   xmm0, qword ptr [rsp]
        vmovss   dword ptr [rax+0x08], xmm0
        lea      rdi, bword ptr [rbx+0x10]
        mov      rsi, rax
        call     CORINFO_HELP_ASSIGN_REF
        mov      rdi, r15
        call     CORINFO_HELP_NEWSFAST
-       vmovss   xmm0, dword ptr [rsp+0x04]
-       vmovss   dword ptr [rax+0x08], xmm0
+       vmovsd   xmm0, qword ptr [rsp]
+       vextractps dword ptr [rax+0x08], xmm0, 1
        lea      rdi, bword ptr [rbx+0x18]
        mov      rsi, rax
        call     CORINFO_HELP_ASSIGN_REF
        lea      rdx, bword ptr [rbx+0x10]
        mov      ecx, 2
        mov      rdi, 0xD1FFAB1E      ; const ptr
        mov      rdi, gword ptr [rdi]
        mov      rsi, 0xD1FFAB1E      ; 'HalfVector2({0:#0.##}, {1:#0.##})'
        mov      rax, 0xD1FFAB1E      ; code for System.String:FormatHelper(System.IFormatProvider,System.String,System.ReadOnlySpan`1[System.Object]):System.String
-						;; size=176 bbWeight=1 PerfScore 36.25
+						;; size=183 bbWeight=1 PerfScore 40.25
 G_M19285_IG03:
        add      rsp, 8
        pop      rbx
        pop      r15
        tail.jmp [rax]System.String:FormatHelper(System.IFormatProvider,System.String,System.ReadOnlySpan`1[System.Object]):System.String
 						;; size=10 bbWeight=1 PerfScore 3.25
 
-; Total bytes of code 196, prolog size 10, PerfScore 43.75, instruction count 44, allocated bytes for code 196 (MethodHash=88fab4aa) for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToString():System.String:this (FullOpts)
+; Total bytes of code 197, prolog size 4, PerfScore 46.50, instruction count 43, allocated bytes for code 197 (MethodHash=88fab4aa) for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToString():System.String:this (FullOpts)
 ; ============================================================

Note: some changes were skipped as they were too large to fit into a comment.

Larger list of diffs: https://gist.github.com/MihuBot/358f4a52fcf5c567ee0826c50329f529

[MihuBot]

Top method improvements

-20 (-2.07 % of base) - BepuPhysics.Trees.Tree:Add[byte](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this

 ; Assembly listing for method BepuPhysics.Trees.Tree:Add[byte](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
 ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
 ; FullOpts code
 ; optimized code
 ; rbp based frame
 ; fully interruptible
 ; No PGO data
 ; 0 inlinees with PGO data; 31 single block inlinees; 2 inlinees without PGO data
 ; Final local variable assignments
 ;
 ;  V00 this         [V00,T04] ( 23, 17.50)   byref  ->  rbx         this single-def
-;  V01 arg1         [V01,T29] (  3,  1.50)  struct (32) [rbp+0x10]  do-not-enreg[S] ld-addr-op single-def <BepuUtilities.BoundingBox>
+;  V01 arg1         [V01,T22] (  4,  2   )  struct (32) [rbp+0x10]  do-not-enreg[SF] ld-addr-op single-def <BepuUtilities.BoundingBox>
 ;  V02 arg2         [V02,T18] (  3,  2.50)     ref  ->  rsi         class-hnd single-def <BepuUtilities.Memory.BufferPool>
 ;  V03 loc0         [V03,T13] (  4,  9   )     int  ->  rax        
-;  V04 loc1         [V04    ] (  6, 17   )  struct (32) [rbp-0x30]  do-not-enreg[SF] ld-addr-op <BepuUtilities.BoundingBox4>
-;  V05 loc2         [V05,T22] (  4,  2   )     int  ->  rcx        
+;* V04 loc1         [V04    ] (  0,  0   )  struct (32) zero-ref    do-not-enreg[SF] ld-addr-op <BepuUtilities.BoundingBox4>
+;  V05 loc2         [V05,T23] (  4,  2   )     int  ->  rcx        
 ;  V06 loc3         [V06,T30] (  3,  1.50)     int  ->  rdx        
 ;  V07 loc4         [V07,T21] (  4,  2   )   byref  ->  rax         single-def
 ;* V08 loc5         [V08    ] (  0,  0   )     int  ->  zero-ref   
 ;  V09 loc6         [V09,T00] ( 10, 36   )   byref  ->  rsi        
-;  V10 loc7         [V10    ] (  5, 18   )  struct (32) [rbp-0x50]  do-not-enreg[XSF] addr-exposed ld-addr-op <BepuUtilities.BoundingBox4>
-;  V11 loc8         [V11    ] (  5, 18   )  struct (32) [rbp-0x70]  do-not-enreg[XSF] addr-exposed ld-addr-op <BepuUtilities.BoundingBox4>
-;  V12 loc9         [V12,T65] (  3, 10   )   float  ->  mm2        
-;  V13 loc10        [V13,T66] (  3, 10   )   float  ->  mm3        
+;  V10 loc7         [V10    ] (  5, 18   )  struct (32) [rbp-0x30]  do-not-enreg[XSF] addr-exposed ld-addr-op <BepuUtilities.BoundingBox4>
+;  V11 loc8         [V11    ] (  5, 18   )  struct (32) [rbp-0x50]  do-not-enreg[XSF] addr-exposed ld-addr-op <BepuUtilities.BoundingBox4>
+;  V12 loc9         [V12,T64] (  3, 10   )   float  ->  mm3        
+;  V13 loc10        [V13,T65] (  3, 10   )   float  ->  mm4        
 ;  V14 loc11        [V14,T15] (  3,  8.50)   ubyte  ->   r9        
 ;* V15 loc12        [V15    ] (  0,  0   )   byref  ->  zero-ref   
 ;* V16 loc13        [V16    ] (  0,  0   )   byref  ->  zero-ref   
 ;  V17 loc14        [V17,T20] (  5,  2.50)   byref  ->  r11         single-def
-;  V18 loc15        [V18,T28] (  3,  1.50)   byref  ->   r8         single-def
+;  V18 loc15        [V18,T29] (  3,  1.50)   byref  ->   r8         single-def
 ;  V19 loc16        [V19,T09] (  3, 12   )     int  ->  rax        
 ;  V20 loc17        [V20,T17] (  2,  8   )     int  ->   r8        
 ;* V21 loc18        [V21    ] (  0,  0   )     int  ->  zero-ref   
 ;# V22 OutArgs      [V22    ] (  1,  1   )  struct ( 0) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
-;  V23 tmp1         [V23,T55] (  2, 16   )   float  ->  mm2         "impAppendStmt"
-;  V24 tmp2         [V24,T56] (  2, 16   )   float  ->  mm3         "impAppendStmt"
+;  V23 tmp1         [V23,T54] (  2, 16   )   float  ->  mm3         "impAppendStmt"
+;  V24 tmp2         [V24,T55] (  2, 16   )   float  ->  mm4         "impAppendStmt"
 ;  V25 tmp3         [V25,T16] (  3,  8   )     int  ->   r9        
 ;  V26 tmp4         [V26,T14] (  4,  8.50)   byref  ->  r10        
 ;  V27 tmp5         [V27,T02] ( 12, 26.50)   byref  ->  rsi        
 ;* V28 tmp6         [V28    ] (  0,  0   )   byref  ->  zero-ref    "impAppendStmt"
 ;* V29 tmp7         [V29    ] (  0,  0   )   byref  ->  zero-ref    "impAppendStmt"
 ;* V30 tmp8         [V30    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <BepuPhysics.Trees.Leaf>
-;  V31 tmp9         [V31,T24] (  2,  2   )   byref  ->  rax         single-def "impAppendStmt"
+;  V31 tmp9         [V31,T25] (  2,  2   )   byref  ->  rax         single-def "impAppendStmt"
 ;* V32 tmp10        [V32    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V33 tmp11        [V33    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
-;  V34 tmp12        [V34,T27] (  2,  2   )     int  ->  rdx         "Inlining Arg"
+;  V34 tmp12        [V34,T28] (  2,  2   )     int  ->  rdx         "Inlining Arg"
 ;* V35 tmp13        [V35    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <BepuPhysics.Trees.Leaf>
-;  V36 tmp14        [V36,T25] (  2,  2   )   byref  ->  rcx         single-def "impAppendStmt"
-;  V37 tmp15        [V37,T23] (  4,  2   )     int  ->  rcx         "Inline stloc first use temp"
+;  V36 tmp14        [V36,T26] (  2,  2   )   byref  ->  rcx         single-def "impAppendStmt"
+;  V37 tmp15        [V37,T24] (  4,  2   )     int  ->  rcx         "Inline stloc first use temp"
 ;* V38 tmp16        [V38    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V39 tmp17        [V39    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;  V40 tmp18        [V40,T31] (  3,  1.50)     int  ->  rcx         "Inline stloc first use temp"
 ;* V41 tmp19        [V41    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <BepuPhysics.Trees.Leaf>
-;  V42 tmp20        [V42,T26] (  2,  2   )   byref  ->  rdx         single-def "impAppendStmt"
+;  V42 tmp20        [V42,T27] (  2,  2   )   byref  ->  rdx         single-def "impAppendStmt"
 ;  V43 tmp21        [V43,T32] (  3,  1.50)     int  ->  rdx         "Inline stloc first use temp"
 ;* V44 tmp22        [V44    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V45 tmp23        [V45    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V46 tmp24        [V46    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V47 tmp25        [V47    ] (  0,  0   )   byref  ->  zero-ref    "Inline stloc first use temp"
 ;* V48 tmp26        [V48    ] (  0,  0   )   byref  ->  zero-ref    "Inline stloc first use temp"
 ;* V49 tmp27        [V49    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V50 tmp28        [V50    ] (  0,  0   )  simd16  ->  zero-ref    "fgMakeTemp is creating a new local variable"
-;  V51 tmp29        [V51,T42] (  3, 24   )  simd16  ->  mm2         "fgMakeTemp is creating a new local variable"
-;  V52 tmp30        [V52,T43] (  3, 24   )  simd16  ->  mm2         "fgMakeTemp is creating a new local variable"
-;  V53 tmp31        [V53,T44] (  3, 24   )  simd16  ->  mm3         "fgMakeTemp is creating a new local variable"
+;  V51 tmp29        [V51,T42] (  3, 24   )  simd16  ->  mm3         "fgMakeTemp is creating a new local variable"
+;* V52 tmp30        [V52    ] (  0,  0   )  simd16  ->  zero-ref    "fgMakeTemp is creating a new local variable"
+;  V53 tmp31        [V53,T43] (  3, 24   )  simd16  ->  mm3         "fgMakeTemp is creating a new local variable"
 ;* V54 tmp32        [V54    ] (  0,  0   )   byref  ->  zero-ref    "Inline stloc first use temp"
 ;* V55 tmp33        [V55    ] (  0,  0   )   byref  ->  zero-ref    "Inline stloc first use temp"
 ;  V56 tmp34        [V56,T03] (  3, 24   )   byref  ->   r9         "Inlining Arg"
 ;* V57 tmp35        [V57    ] (  0,  0   )  simd16  ->  zero-ref    "fgMakeTemp is creating a new local variable"
-;  V58 tmp36        [V58,T45] (  3, 24   )  simd16  ->  mm2         "fgMakeTemp is creating a new local variable"
-;  V59 tmp37        [V59,T46] (  3, 24   )  simd16  ->  mm2         "fgMakeTemp is creating a new local variable"
-;  V60 tmp38        [V60,T47] (  3, 24   )  simd16  ->  mm3         "fgMakeTemp is creating a new local variable"
+;  V58 tmp36        [V58,T44] (  3, 24   )  simd16  ->  mm3         "fgMakeTemp is creating a new local variable"
+;* V59 tmp37        [V59    ] (  0,  0   )  simd16  ->  zero-ref    "fgMakeTemp is creating a new local variable"
+;  V60 tmp38        [V60,T45] (  3, 24   )  simd16  ->  mm3         "fgMakeTemp is creating a new local variable"
 ;* V61 tmp39        [V61    ] (  0,  0   )  struct (32) zero-ref    "Inlining Arg" <BepuUtilities.BoundingBox4>
 ;* V62 tmp40        [V62    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
 ;* V63 tmp41        [V63    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
-;  V64 tmp42        [V64,T48] (  5, 20   )  simd16  ->  mm2         "Inline stloc first use temp" <System.Numerics.Vector4>
-;  V65 tmp43        [V65,T05] (  2, 16   )  struct (32) [rbp-0x90]  do-not-enreg[SF] ld-addr-op "Inlining Arg" <BepuPhysics.Trees.NodeChild>
-;  V66 tmp44        [V66    ] (  5, 40   )  struct (32) [rbp-0xB0]  do-not-enreg[SF] "Inlining Arg" <BepuUtilities.BoundingBox4>
+;  V64 tmp42        [V64,T46] (  5, 20   )  simd16  ->  mm3         "Inline stloc first use temp" <System.Numerics.Vector4>
+;  V65 tmp43        [V65,T05] (  2, 16   )  struct (32) [rbp-0x70]  do-not-enreg[SF] ld-addr-op "Inlining Arg" <BepuPhysics.Trees.NodeChild>
+;  V66 tmp44        [V66    ] (  5, 40   )  struct (32) [rbp-0x90]  do-not-enreg[SF] "Inlining Arg" <BepuUtilities.BoundingBox4>
 ;* V67 tmp45        [V67    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
 ;* V68 tmp46        [V68    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
-;  V69 tmp47        [V69,T49] (  5, 20   )  simd16  ->  mm3         "Inline stloc first use temp" <System.Numerics.Vector4>
+;  V69 tmp47        [V69,T47] (  5, 20   )  simd16  ->  mm4         "Inline stloc first use temp" <System.Numerics.Vector4>
 ;* V70 tmp48        [V70    ] (  0,  0   )  struct (32) zero-ref    "Inlining Arg" <BepuUtilities.BoundingBox4>
 ;* V71 tmp49        [V71    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
 ;* V72 tmp50        [V72    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
-;  V73 tmp51        [V73,T50] (  5, 20   )  simd16  ->  mm3         "Inline stloc first use temp" <System.Numerics.Vector4>
-;  V74 tmp52        [V74,T06] (  2, 16   )  struct (32) [rbp-0xD0]  do-not-enreg[SF] ld-addr-op "Inlining Arg" <BepuPhysics.Trees.NodeChild>
-;  V75 tmp53        [V75    ] (  5, 40   )  struct (32) [rbp-0xF0]  do-not-enreg[SF] "Inlining Arg" <BepuUtilities.BoundingBox4>
+;  V73 tmp51        [V73,T48] (  5, 20   )  simd16  ->  mm4         "Inline stloc first use temp" <System.Numerics.Vector4>
+;  V74 tmp52        [V74,T06] (  2, 16   )  struct (32) [rbp-0xB0]  do-not-enreg[SF] ld-addr-op "Inlining Arg" <BepuPhysics.Trees.NodeChild>
+;  V75 tmp53        [V75    ] (  5, 40   )  struct (32) [rbp-0xD0]  do-not-enreg[SF] "Inlining Arg" <BepuUtilities.BoundingBox4>
 ;* V76 tmp54        [V76    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
 ;* V77 tmp55        [V77    ] (  0,  0   )  simd16  ->  zero-ref    "Inlining Arg" <System.Numerics.Vector4>
-;  V78 tmp56        [V78,T51] (  5, 20   )  simd16  ->  mm4         "Inline stloc first use temp" <System.Numerics.Vector4>
+;  V78 tmp56        [V78,T49] (  5, 20   )  simd16  ->  mm5         "Inline stloc first use temp" <System.Numerics.Vector4>
 ;* V79 tmp57        [V79    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V80 tmp58        [V80    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V81 tmp59        [V81    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
 ;* V82 tmp60        [V82    ] (  0,  0   )     int  ->  zero-ref    "Inlining Arg"
-;  V83 tmp61        [V83,T54] (  6, 17   )  simd16  ->  [rbp-0x30]  do-not-enreg[S] "field V04.Min (fldOffset=0x0)" P-DEP
-;  V84 tmp62        [V84,T67] (  3,  8.50)  simd16  ->  [rbp-0x20]  do-not-enreg[S] "field V04.Max (fldOffset=0x10)" P-DEP
-;  V85 tmp63        [V85    ] (  4, 14   )  simd16  ->  [rbp-0x50]  do-not-enreg[XS] addr-exposed "field V10.Min (fldOffset=0x0)" P-DEP
-;  V86 tmp64        [V86    ] (  4, 14   )  simd16  ->  [rbp-0x40]  do-not-enreg[XS] addr-exposed "field V10.Max (fldOffset=0x10)" P-DEP
-;  V87 tmp65        [V87    ] (  4, 14   )  simd16  ->  [rbp-0x70]  do-not-enreg[XS] addr-exposed "field V11.Min (fldOffset=0x0)" P-DEP
-;  V88 tmp66        [V88    ] (  4, 14   )  simd16  ->  [rbp-0x60]  do-not-enreg[XS] addr-exposed "field V11.Max (fldOffset=0x10)" P-DEP
-;  V89 tmp67        [V89,T36] (  2,  1   )     int  ->  rdi         "field V30.packed (fldOffset=0x0)" P-INDEP
-;  V90 tmp68        [V90,T37] (  2,  1   )     int  ->  rdx         "field V35.packed (fldOffset=0x0)" P-INDEP
-;  V91 tmp69        [V91,T38] (  2,  1   )     int  ->  rsi         "field V41.packed (fldOffset=0x0)" P-INDEP
-;  V92 tmp70        [V92,T69] (  2,  8   )  simd16  ->  mm2         "field V61.Min (fldOffset=0x0)" P-INDEP
-;  V93 tmp71        [V93,T70] (  2,  8   )  simd16  ->  mm3         "field V61.Max (fldOffset=0x10)" P-INDEP
-;  V94 tmp72        [V94,T40] (  4, 24   )  simd16  ->  [rbp-0xB0]  do-not-enreg[S] "field V66.Min (fldOffset=0x0)" P-DEP
-;  V95 tmp73        [V95,T52] (  3, 20   )  simd16  ->  [rbp-0xA0]  do-not-enreg[S] "field V66.Max (fldOffset=0x10)" P-DEP
-;  V96 tmp74        [V96,T71] (  2,  8   )  simd16  ->  mm3         "field V70.Min (fldOffset=0x0)" P-INDEP
-;  V97 tmp75        [V97,T72] (  2,  8   )  simd16  ->  mm4         "field V70.Max (fldOffset=0x10)" P-INDEP
-;  V98 tmp76        [V98,T41] (  4, 24   )  simd16  ->  [rbp-0xF0]  do-not-enreg[S] "field V75.Min (fldOffset=0x0)" P-DEP
-;  V99 tmp77        [V99,T53] (  3, 20   )  simd16  ->  [rbp-0xE0]  do-not-enreg[S] "field V75.Max (fldOffset=0x10)" P-DEP
-;  V100 tmp78       [V100,T73] (  2,  8   )  simd16  ->  mm3         "V65.[000..016)"
+;  V83 tmp61        [V83    ] (  4, 14   )  simd16  ->  [rbp-0x30]  do-not-enreg[XS] addr-exposed "field V10.Min (fldOffset=0x0)" P-DEP
+;  V84 tmp62        [V84    ] (  4, 14   )  simd16  ->  [rbp-0x20]  do-not-enreg[XS] addr-exposed "field V10.Max (fldOffset=0x10)" P-DEP
+;  V85 tmp63        [V85    ] (  4, 14   )  simd16  ->  [rbp-0x50]  do-not-enreg[XS] addr-exposed "field V11.Min (fldOffset=0x0)" P-DEP
+;  V86 tmp64        [V86    ] (  4, 14   )  simd16  ->  [rbp-0x40]  do-not-enreg[XS] addr-exposed "field V11.Max (fldOffset=0x10)" P-DEP
+;  V87 tmp65        [V87,T36] (  2,  1   )     int  ->  rdi         "field V30.packed (fldOffset=0x0)" P-INDEP
+;  V88 tmp66        [V88,T37] (  2,  1   )     int  ->  rdx         "field V35.packed (fldOffset=0x0)" P-INDEP
+;  V89 tmp67        [V89,T38] (  2,  1   )     int  ->  rsi         "field V41.packed (fldOffset=0x0)" P-INDEP
+;  V90 tmp68        [V90,T66] (  2,  8   )  simd16  ->  mm3         "field V61.Min (fldOffset=0x0)" P-INDEP
+;  V91 tmp69        [V91,T67] (  2,  8   )  simd16  ->  mm4         "field V61.Max (fldOffset=0x10)" P-INDEP
+;  V92 tmp70        [V92,T40] (  4, 24   )  simd16  ->  [rbp-0x90]  do-not-enreg[S] "field V66.Min (fldOffset=0x0)" P-DEP
+;  V93 tmp71        [V93,T50] (  3, 20   )  simd16  ->  [rbp-0x80]  do-not-enreg[S] "field V66.Max (fldOffset=0x10)" P-DEP
+;  V94 tmp72        [V94,T68] (  2,  8   )  simd16  ->  mm4         "field V70.Min (fldOffset=0x0)" P-INDEP
+;  V95 tmp73        [V95,T69] (  2,  8   )  simd16  ->  mm5         "field V70.Max (fldOffset=0x10)" P-INDEP
+;  V96 tmp74        [V96,T41] (  4, 24   )  simd16  ->  [rbp-0xD0]  do-not-enreg[S] "field V75.Min (fldOffset=0x0)" P-DEP
+;  V97 tmp75        [V97,T51] (  3, 20   )  simd16  ->  [rbp-0xC0]  do-not-enreg[S] "field V75.Max (fldOffset=0x10)" P-DEP
+;  V98 tmp76        [V98,T52] (  5, 16.50)  simd16  ->  mm0         "V04.[000..016)"
+;  V99 tmp77        [V99,T53] (  5, 16.50)  simd16  ->  mm1         "V04.[016..032)"
+;  V100 tmp78       [V100,T70] (  2,  8   )  simd16  ->  mm4         "V65.[000..016)"
 ;  V101 tmp79       [V101,T10] (  3, 12   )     int  ->  r10         "V65.[028..032)"
-;  V102 tmp80       [V102,T74] (  2,  8   )  simd16  ->  mm4         "V74.[000..016)"
+;  V102 tmp80       [V102,T71] (  2,  8   )  simd16  ->  mm5         "V74.[000..016)"
 ;  V103 tmp81       [V103,T11] (  3, 12   )     int  ->  r11         "V74.[028..032)"
 ;* V104 tmp82       [V104    ] (  0,  0   )   byref  ->  zero-ref    "Spilling address for field-by-field copy"
 ;  V105 tmp83       [V105,T01] (  4, 32   )   byref  ->  r10         "Spilling address for field-by-field copy"
 ;  V106 tmp84       [V106,T19] (  3,  3   )   byref  ->  rax         single-def "Zero offset field obj"
-;  V107 cse0        [V107,T39] (  9, 32.50)  simd16  ->  mm1         hoist "CSE #05: aggressive"
-;  V108 cse1        [V108,T33] (  3,  1.50)     int  ->  rdi         "CSE #23: moderate"
-;  V109 cse2        [V109,T08] (  4, 14   )     int  ->   r9         "CSE #09: aggressive"
-;  V110 cse3        [V110,T12] (  3, 12   )     int  ->   r8         "CSE #21: moderate"
+;  V107 cse0        [V107,T39] (  9, 32.50)  simd16  ->  mm2         hoist "CSE #04: aggressive"
+;  V108 cse1        [V108,T33] (  3,  1.50)     int  ->  rdi         "CSE #22: moderate"
+;  V109 cse2        [V109,T08] (  4, 14   )     int  ->   r9         "CSE #08: aggressive"
+;  V110 cse3        [V110,T12] (  3, 12   )     int  ->   r8         "CSE #20: moderate"
 ;  V111 cse4        [V111,T34] (  3,  1.50)     int  ->  rcx         "CSE #03: moderate"
-;  V112 cse5        [V112,T35] (  3,  1.50)    long  ->   r8         "CSE #22: moderate"
-;  V113 cse6        [V113,T68] (  3,  8.50)  simd16  ->  mm0         hoist "CSE #04: moderate"
-;  V114 cse7        [V114,T07] (  4, 14   )   byref  ->   r8         "CSE #16: aggressive"
-;  V115 cse8        [V115,T57] (  3, 12   )   float  ->  mm4         "CSE #06: moderate"
-;  V116 cse9        [V116,T58] (  3, 12   )   float  ->  mm5         "CSE #07: moderate"
-;  V117 cse10       [V117,T59] (  3, 12   )   float  ->  mm5         "CSE #10: moderate"
-;  V118 cse11       [V118,T60] (  3, 12   )   float  ->  mm6         "CSE #11: moderate"
-;  V119 cse12       [V119,T61] (  3, 12   )   float  ->  mm5         "CSE #13: moderate"
-;  V120 cse13       [V120,T62] (  3, 12   )   float  ->  mm6         "CSE #14: moderate"
-;  V121 cse14       [V121,T63] (  3, 12   )   float  ->  mm6         "CSE #17: moderate"
-;  V122 cse15       [V122,T64] (  3, 12   )   float  ->  mm7         "CSE #18: moderate"
+;  V112 cse5        [V112,T35] (  3,  1.50)    long  ->   r8         "CSE #21: moderate"
+;  V113 cse6        [V113,T07] (  4, 14   )   byref  ->   r8         "CSE #15: aggressive"
+;  V114 cse7        [V114,T56] (  3, 12   )   float  ->  mm5         "CSE #05: moderate"
+;  V115 cse8        [V115,T57] (  3, 12   )   float  ->  mm6         "CSE #06: moderate"
+;  V116 cse9        [V116,T58] (  3, 12   )   float  ->  mm6         "CSE #09: moderate"
+;  V117 cse10       [V117,T59] (  3, 12   )   float  ->  mm7         "CSE #10: moderate"
+;  V118 cse11       [V118,T60] (  3, 12   )   float  ->  mm6         "CSE #12: moderate"
+;  V119 cse12       [V119,T61] (  3, 12   )   float  ->  mm7         "CSE #13: moderate"
+;  V120 cse13       [V120,T62] (  3, 12   )   float  ->  mm7         "CSE #16: moderate"
+;  V121 cse14       [V121,T63] (  3, 12   )   float  ->  mm8         "CSE #17: moderate"
 ;
-; Lcl frame size = 224
+; Lcl frame size = 192
 
 G_M20571_IG01:
        push     rbp
        push     r15
        push     rbx
-       sub      rsp, 224
-       lea      rbp, [rsp+0xF0]
+       sub      rsp, 192
+       lea      rbp, [rsp+0xD0]
        mov      rbx, rdi
 						;; size=22 bbWeight=1 PerfScore 4.00
 G_M20571_IG02:
        mov      edx, dword ptr [rbx+0x28]
        cmp      edx, dword ptr [rbx+0x34]
        jne      SHORT G_M20571_IG04
 						;; size=8 bbWeight=1 PerfScore 5.00
 G_M20571_IG03:
        mov      edx, dword ptr [rbx+0x34]
        inc      edx
        mov      rdi, rbx
        mov      rax, 0xD1FFAB1E      ; code for BepuPhysics.Trees.Tree:Resize(BepuUtilities.Memory.BufferPool,int):this
        call     [rax]BepuPhysics.Trees.Tree:Resize(BepuUtilities.Memory.BufferPool,int):this
 						;; size=20 bbWeight=0.50 PerfScore 2.88
 G_M20571_IG04:
        cmp      dword ptr [rbx+0x34], 2
        jl       G_M20571_IG17
 						;; size=10 bbWeight=1 PerfScore 3.00
 G_M20571_IG05:
        xor      eax, eax
-       vmovdqu  ymm0, ymmword ptr [rbp+0x10]
-       vmovdqu  ymmword ptr [rbp-0x30], ymm0
+       vmovups  xmm0, xmmword ptr [rbp+0x10]
+       vmovups  xmm1, xmmword ptr [rbp+0x20]
        mov      ecx, dword ptr [rbx+0x30]
        lea      edx, [rcx+0x01]
        mov      dword ptr [rbx+0x30], edx
        mov      rdx, qword ptr [rbx+0x20]
        movsxd   rdi, dword ptr [rbx+0x34]
        lea      rdx, [rdx+4*rdi]
        mov      edi, ecx
        and      edi, 0xD1FFAB1E
        mov      esi, edi
        mov      dword ptr [rdx], esi
        mov      edx, dword ptr [rbx+0x34]
        lea      esi, [rdx+0x01]
        mov      dword ptr [rbx+0x34], esi
-       vmovaps  xmm0, xmmword ptr [rbp-0x30]
-       vbroadcastss xmm1, dword ptr [reloc @RWD00]
+       vbroadcastss xmm2, dword ptr [reloc @RWD00]
        jmp      SHORT G_M20571_IG07
        align    [0 bytes for IG06]
-						;; size=70 bbWeight=0.50 PerfScore 10.75
+						;; size=65 bbWeight=0.50 PerfScore 9.75
 G_M20571_IG06:
        mov      eax, dword ptr [rsi+0x0C]
        inc      r8d
-       vmovdqu  ymm2, ymmword ptr [r10]
-       vmovdqu  ymmword ptr [rsi], ymm2
+       vmovdqu  ymm3, ymmword ptr [r10]
+       vmovdqu  ymmword ptr [rsi], ymm3
        mov      dword ptr [rsi+0x0C], eax
        mov      dword ptr [rsi+0x1C], r8d
 						;; size=22 bbWeight=4 PerfScore 33.00
 G_M20571_IG07:
        movsxd   rsi, eax
        shl      rsi, 6
        add      rsi, qword ptr [rbx]
-       vmovups  xmm2, xmmword ptr [rsi]
-       vrangeps xmm3, xmm0, xmm2, 4
-       vmovaps  xmm4, xmmword ptr [rbp-0x30]
-       vfixupimmps xmm4, xmm2, xmm1, 0
-       vfixupimmps xmm3, xmm4, xmm1, 0
-       vmovups  xmmword ptr [rbp-0x50], xmm3
-       vmovups  xmm2, xmmword ptr [rbp-0x20]
+       vmovups  xmm3, xmmword ptr [rsi]
+       vrangeps xmm4, xmm0, xmm3, 4
+       vmovaps  xmm5, xmm0
+       vfixupimmps xmm5, xmm3, xmm2, 0
+       vfixupimmps xmm4, xmm5, xmm2, 0
+       vmovups  xmmword ptr [rbp-0x30], xmm4
        vmovups  xmm3, xmmword ptr [rsi+0x10]
-       vrangeps xmm4, xmm2, xmm3, 5
-       vfixupimmps xmm2, xmm3, xmm1, 0
-       vfixupimmps xmm4, xmm2, xmm1, 0
-       vmovups  xmmword ptr [rbp-0x40], xmm4
+       vrangeps xmm4, xmm1, xmm3, 5
+       vmovaps  xmm5, xmm1
+       vfixupimmps xmm5, xmm3, xmm2, 0
+       vfixupimmps xmm4, xmm5, xmm2, 0
+       vmovups  xmmword ptr [rbp-0x20], xmm4
        lea      r8, bword ptr [rsi+0x20]
        mov      r9, r8
-       vmovups  xmm2, xmmword ptr [r9]
-       vrangeps xmm3, xmm0, xmm2, 4
-       vmovaps  xmm4, xmmword ptr [rbp-0x30]
-       vfixupimmps xmm4, xmm2, xmm1, 0
-       vfixupimmps xmm3, xmm4, xmm1, 0
-       vmovups  xmmword ptr [rbp-0x70], xmm3
-       vmovups  xmm2, xmmword ptr [rbp-0x20]
+       vmovups  xmm3, xmmword ptr [r9]
+       vrangeps xmm4, xmm0, xmm3, 4
+       vmovaps  xmm5, xmm0
+       vfixupimmps xmm5, xmm3, xmm2, 0
+       vfixupimmps xmm4, xmm5, xmm2, 0
+       vmovups  xmmword ptr [rbp-0x50], xmm4
        vmovups  xmm3, xmmword ptr [r9+0x10]
-       vrangeps xmm4, xmm2, xmm3, 5
-       vfixupimmps xmm2, xmm3, xmm1, 0
-       vfixupimmps xmm4, xmm2, xmm1, 0
-       vmovups  xmmword ptr [rbp-0x60], xmm4
-       vmovaps  xmm2, xmmword ptr [rbp-0x50]
-       vmovaps  xmm3, xmmword ptr [rbp-0x40]
-       vsubps   xmm2, xmm3, xmm2
-       vmovaps  xmm3, xmm2
-       vmovshdup xmm4, xmm2
-       vmulss   xmm3, xmm3, xmm4
-       vunpckhps xmm5, xmm2, xmm2
-       vmulss   xmm4, xmm4, xmm5
-       vaddss   xmm3, xmm3, xmm4
-       vmulss   xmm2, xmm5, xmm2
-       vaddss   xmm2, xmm3, xmm2
-       mov      r9d, dword ptr [rsi+0x1C]
-       lea      r10d, [r9+0x01]
-       vxorps   xmm3, xmm3, xmm3
-       vcvtsi2ss xmm3, xmm3, r10d
-       vmulss   xmm2, xmm2, xmm3
-       vmovups  xmm3, xmmword ptr [rsi]
-       mov      r10d, r9d
-       vmovdqu  ymm4, ymmword ptr [rsi]
-       vmovdqu  ymmword ptr [rbp-0x90], ymm4
-       vmovdqu  ymm4, ymmword ptr [rbp-0x90]
-       vmovdqu  ymmword ptr [rbp-0xB0], ymm4
-       vmovaps  xmmword ptr [rbp-0xB0], xmm3
-       mov      dword ptr [rbp-0x94], r10d
-       vmovaps  xmm3, xmmword ptr [rbp-0xA0]
-       vsubps   xmm3, xmm3, xmmword ptr [rbp-0xB0]
-       vmovaps  xmm4, xmm3
-       vmovshdup xmm5, xmm3
-       vmulss   xmm4, xmm4, xmm5
-       vunpckhps xmm6, xmm3, xmm3
-       vmulss   xmm5, xmm5, xmm6
-       vaddss   xmm4, xmm4, xmm5
-						;; size=315 bbWeight=4 PerfScore 472.33
-G_M20571_IG08:
-       vmulss   xmm3, xmm6, xmm3
-       vaddss   xmm3, xmm4, xmm3
-       vxorps   xmm4, xmm4, xmm4
-       vcvtsi2ss xmm4, xmm4, r10d
-       vmulss   xmm3, xmm3, xmm4
-       vsubss   xmm2, xmm2, xmm3
-       vmovaps  xmm3, xmmword ptr [rbp-0x70]
-       vmovaps  xmm4, xmmword ptr [rbp-0x60]
+       vrangeps xmm4, xmm1, xmm3, 5
+       vmovaps  xmm5, xmm1
+       vfixupimmps xmm5, xmm3, xmm2, 0
+       vfixupimmps xmm4, xmm5, xmm2, 0
+       vmovups  xmmword ptr [rbp-0x40], xmm4
+       vmovaps  xmm3, xmmword ptr [rbp-0x30]
+       vmovaps  xmm4, xmmword ptr [rbp-0x20]
        vsubps   xmm3, xmm4, xmm3
        vmovaps  xmm4, xmm3
        vmovshdup xmm5, xmm3
        vmulss   xmm4, xmm4, xmm5
        vunpckhps xmm6, xmm3, xmm3
        vmulss   xmm5, xmm5, xmm6
        vaddss   xmm4, xmm4, xmm5
        vmulss   xmm3, xmm6, xmm3
        vaddss   xmm3, xmm4, xmm3
-       mov      r10d, dword ptr [rsi+0x3C]
-       inc      r10d
+       mov      r9d, dword ptr [rsi+0x1C]
+       lea      r10d, [r9+0x01]
        vxorps   xmm4, xmm4, xmm4
        vcvtsi2ss xmm4, xmm4, r10d
        vmulss   xmm3, xmm3, xmm4
-       mov      r10, r8
-       vmovups  xmm4, xmmword ptr [r10]
-       mov      r11d, dword ptr [r10+0x1C]
-       vmovdqu  ymm5, ymmword ptr [r10]
-       vmovdqu  ymmword ptr [rbp-0xD0], ymm5
-       vmovdqu  ymm5, ymmword ptr [rbp-0xD0]
-       vmovdqu  ymmword ptr [rbp-0xF0], ymm5
-       vmovaps  xmmword ptr [rbp-0xF0], xmm4
-       mov      dword ptr [rbp-0xD4], r11d
-       vmovaps  xmm4, xmmword ptr [rbp-0xE0]
-       vsubps   xmm4, xmm4, xmmword ptr [rbp-0xF0]
+       vmovups  xmm4, xmmword ptr [rsi]
+       mov      r10d, r9d
+       vmovdqu  ymm5, ymmword ptr [rsi]
+       vmovdqu  ymmword ptr [rbp-0x70], ymm5
+       vmovdqu  ymm5, ymmword ptr [rbp-0x70]
+       vmovdqu  ymmword ptr [rbp-0x90], ymm5
+       vmovaps  xmmword ptr [rbp-0x90], xmm4
+       mov      dword ptr [rbp-0x74], r10d
+       vmovaps  xmm4, xmmword ptr [rbp-0x80]
+       vsubps   xmm4, xmm4, xmmword ptr [rbp-0x90]
        vmovaps  xmm5, xmm4
        vmovshdup xmm6, xmm4
        vmulss   xmm5, xmm5, xmm6
        vunpckhps xmm7, xmm4, xmm4
        vmulss   xmm6, xmm6, xmm7
        vaddss   xmm5, xmm5, xmm6
        vmulss   xmm4, xmm7, xmm4
        vaddss   xmm4, xmm5, xmm4
+						;; size=308 bbWeight=4 PerfScore 484.33
+G_M20571_IG08:
        vxorps   xmm5, xmm5, xmm5
-       vcvtsi2ss xmm5, xmm5, r11d
+       vcvtsi2ss xmm5, xmm5, r10d
        vmulss   xmm4, xmm4, xmm5
        vsubss   xmm3, xmm3, xmm4
-       vucomiss xmm2, xmm3
+       vmovaps  xmm4, xmmword ptr [rbp-0x50]
+       vmovaps  xmm5, xmmword ptr [rbp-0x40]
+       vsubps   xmm4, xmm5, xmm4
+       vmovaps  xmm5, xmm4
+       vmovshdup xmm6, xmm4
+       vmulss   xmm5, xmm5, xmm6
+       vunpckhps xmm7, xmm4, xmm4
+       vmulss   xmm6, xmm6, xmm7
+       vaddss   xmm5, xmm5, xmm6
+       vmulss   xmm4, xmm7, xmm4
+       vaddss   xmm4, xmm5, xmm4
+       mov      r10d, dword ptr [rsi+0x3C]
+       inc      r10d
+       vxorps   xmm5, xmm5, xmm5
+       vcvtsi2ss xmm5, xmm5, r10d
+       vmulss   xmm4, xmm4, xmm5
+       mov      r10, r8
+       vmovups  xmm5, xmmword ptr [r10]
+       mov      r11d, dword ptr [r10+0x1C]
+       vmovdqu  ymm6, ymmword ptr [r10]
+       vmovdqu  ymmword ptr [rbp-0xB0], ymm6
+       vmovdqu  ymm6, ymmword ptr [rbp-0xB0]
+       vmovdqu  ymmword ptr [rbp-0xD0], ymm6
+       vmovaps  xmmword ptr [rbp-0xD0], xmm5
+       mov      dword ptr [rbp-0xB4], r11d
+       vmovaps  xmm5, xmmword ptr [rbp-0xC0]
+       vsubps   xmm5, xmm5, xmmword ptr [rbp-0xD0]
+       vmovaps  xmm6, xmm5
+       vmovshdup xmm7, xmm5
+       vmulss   xmm6, xmm6, xmm7
+       vunpckhps xmm8, xmm5, xmm5
+       vmulss   xmm7, xmm8, xmm7
+       vaddss   xmm6, xmm6, xmm7
+       vmulss   xmm5, xmm8, xmm5
+       vaddss   xmm5, xmm6, xmm5
+       vxorps   xmm6, xmm6, xmm6
+       vcvtsi2ss xmm6, xmm6, r11d
+       vmulss   xmm5, xmm5, xmm6
+       vsubss   xmm4, xmm4, xmm5
+       vucomiss xmm3, xmm4
        jp       SHORT G_M20571_IG10
        jne      SHORT G_M20571_IG10
-						;; size=217 bbWeight=4 PerfScore 420.00
+						;; size=209 bbWeight=4 PerfScore 396.00
 G_M20571_IG09:
        cmp      r9d, dword ptr [rsi+0x3C]
        setl     r9b
        movzx    r9, r9b
        jmp      SHORT G_M20571_IG11
 						;; size=14 bbWeight=2 PerfScore 9.50
 G_M20571_IG10:
-       vucomiss xmm3, xmm2
+       vucomiss xmm4, xmm3
        seta     r9b
        movzx    r9, r9b
 						;; size=12 bbWeight=2 PerfScore 5.50
 G_M20571_IG11:
        test     r9d, r9d
        je       SHORT G_M20571_IG13
 						;; size=5 bbWeight=4 PerfScore 5.00
 G_M20571_IG12:
-       lea      r10, bword ptr [rbp-0x50]
+       lea      r10, bword ptr [rbp-0x30]
        jmp      SHORT G_M20571_IG14
 						;; size=6 bbWeight=2 PerfScore 5.00
 G_M20571_IG13:
-       lea      r10, bword ptr [rbp-0x70]
+       lea      r10, bword ptr [rbp-0x50]
        mov      rsi, r8
 						;; size=7 bbWeight=2 PerfScore 1.50
 G_M20571_IG14:
        mov      r8d, dword ptr [rsi+0x1C]
        cmp      r8d, 1
        jne      G_M20571_IG06
 						;; size=14 bbWeight=4 PerfScore 13.00
 G_M20571_IG15:
        movsxd   r8, ecx
        mov      r11, r8
        shl      r11, 6
        add      r11, qword ptr [rbx]
        mov      r15, qword ptr [rbx+0x10]
        lea      r8, [r8+2*r8]
        lea      r8, [r15+4*r8]
        mov      dword ptr [r8], eax
        test     r9d, r9d
        sete     al
        movzx    rax, al
        mov      dword ptr [r8+0x04], eax
        vmovdqu  ymm0, ymmword ptr [rbp+0x10]
        vmovdqu  ymmword ptr [r11], ymm0
        mov      dword ptr [r11+0x1C], 1
        mov      eax, edx
        not      eax
        mov      dword ptr [r11+0x0C], eax
        vmovdqu  ymm0, ymmword ptr [rsi]
        vmovdqu  ymmword ptr [r11+0x20], ymm0
        mov      rax, qword ptr [rbx+0x20]
        mov      r8d, dword ptr [rsi+0x0C]
        not      r8d
        movsxd   r8, r8d
        lea      rax, [rax+4*r8]
        or       edi, 0xD1FFAB1E
        mov      dword ptr [rax], edi
        vmovdqu  ymm0, ymmword ptr [r10]
        vmovdqu  ymmword ptr [rsi], ymm0
        mov      dword ptr [rsi+0x1C], 2
        mov      dword ptr [rsi+0x0C], ecx
        mov      eax, edx
 						;; size=124 bbWeight=0.50 PerfScore 15.50
 G_M20571_IG16:
        vzeroupper 
-       add      rsp, 224
+       add      rsp, 192
        pop      rbx
        pop      r15
        pop      rbp
        ret      
 						;; size=15 bbWeight=0.50 PerfScore 1.88
 G_M20571_IG17:
        mov      rax, bword ptr [rbx]
        cmp      byte  ptr [rax], al
        movsxd   rcx, dword ptr [rbx+0x34]
        shl      rcx, 5
        add      rax, rcx
        vmovdqu  ymm0, ymmword ptr [rbp+0x10]
        vmovdqu  ymmword ptr [rax], ymm0
        mov      ecx, dword ptr [rbx+0x34]
        mov      edx, ecx
        mov      rdi, qword ptr [rbx+0x20]
        movsxd   rcx, ecx
        lea      rcx, [rdi+4*rcx]
        shl      edx, 31
        mov      dword ptr [rcx], edx
        mov      ecx, dword ptr [rbx+0x34]
        lea      edx, [rcx+0x01]
        mov      dword ptr [rbx+0x34], edx
        mov      edx, ecx
        not      edx
        mov      dword ptr [rax+0x0C], edx
        mov      dword ptr [rax+0x1C], 1
        mov      eax, ecx
 						;; size=71 bbWeight=0.50 PerfScore 11.25
 G_M20571_IG18:
        vzeroupper 
-       add      rsp, 224
+       add      rsp, 192
        pop      rbx
        pop      r15
        pop      rbp
        ret      
 						;; size=15 bbWeight=0.50 PerfScore 1.88
 RWD00  	dd	00000001h		; 1.4013e-45
 
 
-; Total bytes of code 967, prolog size 22, PerfScore 1020.96, instruction count 233, allocated bytes for code 967 (MethodHash=7ddcafa4) for method BepuPhysics.Trees.Tree:Add[byte](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
+; Total bytes of code 947, prolog size 22, PerfScore 1007.96, instruction count 232, allocated bytes for code 947 (MethodHash=7ddcafa4) for method BepuPhysics.Trees.Tree:Add[byte](BepuUtilities.BoundingBox,BepuUtilities.Memory.BufferPool):int:this (FullOpts)
 ; ============================================================

-9 (-17.65 % of base) - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector2():System.Numerics.Vector2:this

 ; Assembly listing for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector2():System.Numerics.Vector2:this (FullOpts)
 ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
 ; FullOpts code
 ; optimized code
 ; rsp based frame
 ; partially interruptible
 ; No PGO data
 ; 0 inlinees with PGO data; 8 single block inlinees; 0 inlinees without PGO data
 ; Final local variable assignments
 ;
 ;  V00 this         [V00,T00] (  4,  4   )   byref  ->  rdi         this single-def
-;* V01 loc0         [V01    ] (  0,  0   )   simd8  ->  zero-ref    ld-addr-op <System.Numerics.Vector2>
+;  V01 loc0         [V01,T03] (  2,  2   )   simd8  ->  mm0         ld-addr-op single-def <System.Numerics.Vector2>
 ;# V02 OutArgs      [V02    ] (  1,  1   )  struct ( 0) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
 ;* V03 tmp1         [V03    ] (  0,  0   )  ushort  ->  zero-ref    "Inlining Arg"
 ;* V04 tmp2         [V04    ] (  0,  0   )  struct ( 8) zero-ref    "System.Half tmp" <System.Half>
 ;* V05 tmp3         [V05    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <System.Half>
 ;* V06 tmp4         [V06    ] (  0,  0   )  ushort  ->  zero-ref    "Inlining Arg"
 ;* V07 tmp5         [V07    ] (  0,  0   )  struct ( 8) zero-ref    "System.Half tmp" <System.Half>
 ;* V08 tmp6         [V08    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <System.Half>
-;  V09 tmp7         [V09,T04] (  2,  2   )   float  ->  mm0         single-def "field V01.X (fldOffset=0x0)" P-INDEP
-;  V10 tmp8         [V10,T05] (  2,  2   )   float  ->  mm1         single-def "field V01.Y (fldOffset=0x4)" P-INDEP
-;* V11 tmp9         [V11    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V04._value (fldOffset=0x0)" P-INDEP
-;  V12 tmp10        [V12,T01] (  2,  2   )  ushort  ->  rax         single-def "field V05._value (fldOffset=0x0)" P-INDEP
-;* V13 tmp11        [V13    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V07._value (fldOffset=0x0)" P-INDEP
-;  V14 tmp12        [V14,T02] (  2,  2   )  ushort  ->  rax         single-def "field V08._value (fldOffset=0x0)" P-INDEP
-;  V15 rat0         [V15,T03] (  3,  6   )   simd8  ->  [rsp+0x00]  do-not-enreg[SF] "Spilled local for field list" <System.Numerics.Vector2>
+;* V09 tmp7         [V09    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V04._value (fldOffset=0x0)" P-INDEP
+;  V10 tmp8         [V10,T01] (  2,  2   )  ushort  ->  rax         single-def "field V05._value (fldOffset=0x0)" P-INDEP
+;* V11 tmp9         [V11    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V07._value (fldOffset=0x0)" P-INDEP
+;  V12 tmp10        [V12,T02] (  2,  2   )  ushort  ->  rax         single-def "field V08._value (fldOffset=0x0)" P-INDEP
 ;
-; Lcl frame size = 8
+; Lcl frame size = 0
 
 G_M45955_IG01:
-       push     rax
-						;; size=1 bbWeight=1 PerfScore 1.00
+						;; size=0 bbWeight=1 PerfScore 0.00
 G_M45955_IG02:
        movzx    rax, word  ptr [rdi]
        vmovd    xmm0, eax
        vcvtph2ps xmm0, xmm0
+       vinsertps xmm0, xmm0, xmm0, 14
        mov      eax, dword ptr [rdi]
        shr      eax, 16
        movzx    rax, ax
        vmovd    xmm1, eax
        vcvtph2ps xmm1, xmm1
-       vmovss   dword ptr [rsp], xmm0
-       vmovss   dword ptr [rsp+0x04], xmm1
-       vmovsd   xmm0, qword ptr [rsp]
-						;; size=45 bbWeight=1 PerfScore 20.75
+       vinsertps xmm0, xmm0, xmm1, 16
+						;; size=41 bbWeight=1 PerfScore 18.75
 G_M45955_IG03:
-       add      rsp, 8
        ret      
-						;; size=5 bbWeight=1 PerfScore 1.25
+						;; size=1 bbWeight=1 PerfScore 1.00
 
-; Total bytes of code 51, prolog size 1, PerfScore 23.00, instruction count 14, allocated bytes for code 51 (MethodHash=3fd74c7c) for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector2():System.Numerics.Vector2:this (FullOpts)
+; Total bytes of code 42, prolog size 0, PerfScore 19.75, instruction count 11, allocated bytes for code 42 (MethodHash=3fd74c7c) for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector2():System.Numerics.Vector2:this (FullOpts)
 ; ============================================================

-9 (-11.39 % of base) - SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector4():System.Numerics.Vector4:this

 ; Assembly listing for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector4():System.Numerics.Vector4:this (FullOpts)
 ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
 ; FullOpts code
 ; optimized code
 ; rsp based frame
 ; partially interruptible
 ; No PGO data
 ; 0 inlinees with PGO data; 11 single block inlinees; 0 inlinees without PGO data
 ; Final local variable assignments
 ;
 ;  V00 this         [V00,T00] (  4,  4   )   byref  ->  rdi         this single-def
-;* V01 loc0         [V01    ] (  0,  0   )   simd8  ->  zero-ref    single-def <System.Numerics.Vector2>
+;  V01 loc0         [V01,T04] (  3,  3   )   simd8  ->  mm0         single-def <System.Numerics.Vector2>
 ;# V02 OutArgs      [V02    ] (  1,  1   )  struct ( 0) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
 ;  V03 tmp1         [V03,T03] (  2,  4   )  simd16  ->  mm0         multireg-ret ld-addr-op "NewObj constructor temp" <System.Numerics.Vector4>
-;  V04 tmp2         [V04    ] (  4,  4   )   simd8  ->  [rsp+0x00]  do-not-enreg[SB] must-init ld-addr-op "Inline ldloca(s) first use temp" <System.Numerics.Vector2>
+;  V04 tmp2         [V04,T05] (  2,  2   )   simd8  ->  mm0         ld-addr-op single-def "Inline ldloca(s) first use temp" <System.Numerics.Vector2>
 ;* V05 tmp3         [V05    ] (  0,  0   )  ushort  ->  zero-ref    "Inlining Arg"
 ;* V06 tmp4         [V06    ] (  0,  0   )  struct ( 8) zero-ref    "System.Half tmp" <System.Half>
 ;* V07 tmp5         [V07    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <System.Half>
 ;* V08 tmp6         [V08    ] (  0,  0   )  ushort  ->  zero-ref    "Inlining Arg"
 ;* V09 tmp7         [V09    ] (  0,  0   )  struct ( 8) zero-ref    "System.Half tmp" <System.Half>
 ;* V10 tmp8         [V10    ] (  0,  0   )  struct ( 8) zero-ref    ld-addr-op "NewObj constructor temp" <System.Half>
 ;* V11 tmp9         [V11    ] (  0,  0   )   float  ->  zero-ref    "Inlining Arg"
 ;* V12 tmp10        [V12    ] (  0,  0   )   float  ->  zero-ref    "Inlining Arg"
 ;* V13 tmp11        [V13    ] (  0,  0   )   float  ->  zero-ref    "Inlining Arg"
 ;* V14 tmp12        [V14    ] (  0,  0   )   float  ->  zero-ref    "Inlining Arg"
-;  V15 tmp13        [V15,T04] (  3,  3   )   float  ->  [rsp+0x00]  do-not-enreg[] "field V04.X (fldOffset=0x0)" P-DEP
-;  V16 tmp14        [V16,T05] (  3,  3   )   float  ->  [rsp+0x04]  do-not-enreg[] "field V04.Y (fldOffset=0x4)" P-DEP
-;* V17 tmp15        [V17    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V06._value (fldOffset=0x0)" P-INDEP
-;  V18 tmp16        [V18,T01] (  2,  2   )  ushort  ->  rax         single-def "field V07._value (fldOffset=0x0)" P-INDEP
-;* V19 tmp17        [V19    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V09._value (fldOffset=0x0)" P-INDEP
-;  V20 tmp18        [V20,T02] (  2,  2   )  ushort  ->  rax         single-def "field V10._value (fldOffset=0x0)" P-INDEP
+;* V15 tmp13        [V15    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V06._value (fldOffset=0x0)" P-INDEP
+;  V16 tmp14        [V16,T01] (  2,  2   )  ushort  ->  rax         single-def "field V07._value (fldOffset=0x0)" P-INDEP
+;* V17 tmp15        [V17    ] (  0,  0   )  ushort  ->  zero-ref    single-def "field V09._value (fldOffset=0x0)" P-INDEP
+;  V18 tmp16        [V18,T02] (  2,  2   )  ushort  ->  rax         single-def "field V10._value (fldOffset=0x0)" P-INDEP
 ;
-; Lcl frame size = 8
+; Lcl frame size = 0
 
 G_M32771_IG01:
-       push     rax
-       xor      eax, eax
-       mov      qword ptr [rsp], rax
-						;; size=7 bbWeight=1 PerfScore 2.25
+						;; size=0 bbWeight=1 PerfScore 0.00
 G_M32771_IG02:
        movzx    rax, word  ptr [rdi]
        vmovd    xmm0, eax
        vcvtph2ps xmm0, xmm0
-       vmovss   dword ptr [rsp], xmm0
+       vinsertps xmm0, xmm0, xmm0, 14
        mov      eax, dword ptr [rdi]
        shr      eax, 16
        movzx    rax, ax
-       vmovd    xmm0, eax
-       vcvtph2ps xmm0, xmm0
-       vmovss   dword ptr [rsp+0x04], xmm0
-       vmovss   xmm0, dword ptr [rsp]
-       vinsertps xmm0, xmm0, dword ptr [rsp+0x04], 20
+       vmovd    xmm1, eax
+       vcvtph2ps xmm1, xmm1
+       vinsertps xmm0, xmm0, xmm1, 16
+       vmovaps  xmm1, xmm0
+       vmovshdup xmm0, xmm0
+       vinsertps xmm0, xmm1, xmm0, 20
        vinsertps xmm0, xmm0, dword ptr [reloc @RWD00], 48
        vmovhlps xmm1, xmm1, xmm0
-						;; size=67 bbWeight=1 PerfScore 25.75
+						;; size=69 bbWeight=1 PerfScore 24.00
 G_M32771_IG03:
-       add      rsp, 8
        ret      
-						;; size=5 bbWeight=1 PerfScore 1.25
+						;; size=1 bbWeight=1 PerfScore 1.00
 RWD00  	dd	3F800000h		;         1
 
 
-; Total bytes of code 79, prolog size 7, PerfScore 29.25, instruction count 19, allocated bytes for code 79 (MethodHash=76047ffc) for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector4():System.Numerics.Vector4:this (FullOpts)
+; Total bytes of code 70, prolog size 0, PerfScore 25.00, instruction count 16, allocated bytes for code 70 (MethodHash=76047ffc) for method SixLabors.ImageSharp.PixelFormats.HalfVector2:ToVector4():System.Numerics.Vector4:this (FullOpts)
 ; ============================================================

-2 (-0.48 % of base) - BepuPhysics.Collidables.ConvexHullWide:RayTest(byref,byref,byref,byref,byref):this

 ; Assembly listing for method BepuPhysics.Collidables.ConvexHullWide:RayTest(byref,byref,byref,byref,byref):this (FullOpts)
 ; Emitting BLENDED_CODE for x64 + VEX + EVEX on Unix
 ; FullOpts code
 ; optimized code
 ; rbp based frame
 ; partially interruptible
 ; No PGO data
 ; 0 inlinees with PGO data; 30 single block inlinees; 0 inlinees without PGO data
 ; Final local variable assignments
 ;
-;  V00 this         [V00,T07] (  4, 14   )   byref  ->  rbx         this single-def
-;  V01 arg1         [V01,T09] (  3,  6   )   byref  ->  r15         single-def
-;  V02 arg2         [V02,T10] (  3,  6   )   byref  ->  r14         single-def
-;  V03 arg3         [V03,T11] (  3,  6   )   byref  ->  r13         single-def
-;  V04 arg4         [V04,T12] (  3,  6   )   byref  ->  r12         single-def
-;  V05 arg5         [V05,T13] (  3,  6   )   byref  ->  [rbp-0xA8]  single-def
+;  V00 this         [V00,T06] (  4, 14   )   byref  ->  rbx         this single-def
+;  V01 arg1         [V01,T08] (  3,  6   )   byref  ->  r15         single-def
+;  V02 arg2         [V02,T09] (  3,  6   )   byref  ->  r14         single-def
+;  V03 arg3         [V03,T10] (  3,  6   )   byref  ->  r13         single-def
+;  V04 arg4         [V04,T11] (  3,  6   )   byref  ->  r12         single-def
+;  V05 arg5         [V05,T12] (  3,  6   )   byref  ->  [rbp-0xA8]  single-def
 ;  V06 loc0         [V06,T04] (  5, 21   )     int  ->  [rbp-0x2C] 
 ;  V07 loc1         [V07    ] (  8, 32   )  struct (32) [rbp-0x50]  do-not-enreg[XSF] addr-exposed ld-addr-op <BepuPhysics.RigidPose>
-;  V08 loc2         [V08,T05] (  5, 20   )   byref  ->  rdi        
-;* V09 loc3         [V09    ] (  0,  0   )  simd12  ->  zero-ref    multireg-arg ld-addr-op <System.Numerics.Vector3>
-;* V10 loc4         [V10    ] (  0,  0   )  simd12  ->  zero-ref    multireg-arg ld-addr-op <System.Numerics.Vector3>
-;  V11 loc5         [V11,T16] (  2,  8   )   ubyte  ->  rax        
-;  V12 loc6         [V12    ] (  2,  8   )   float  ->  [rbp-0x54]  do-not-enreg[X] addr-exposed ld-addr-op
-;  V13 loc7         [V13    ] (  2,  8   )  simd12  ->  [rbp-0x70]  do-not-enreg[XS] addr-exposed ld-addr-op <System.Numerics.Vector3>
+;  V08 loc2         [V08,T03] (  7, 28   )   byref  ->  rdi        
+;  V09 loc3         [V09,T17] (  4, 16   )  simd12  ->  [rbp-0x60]  do-not-enreg[SFA] multireg-arg ld-addr-op <System.Numerics.Vector3>
+;  V10 loc4         [V10,T18] (  4, 16   )  simd12  ->  [rbp-0x70]  do-not-enreg[SFA] multireg-arg ld-addr-op <System.Numerics.Vector3>
+;  V11 loc5         [V11,T15] (  2,  8   )   ubyte  ->  rax        
+;  V12 loc6         [V12    ] (  2,  8   )   float  ->  [rbp-0x74]  do-not-enreg[X] addr-exposed ld-addr-op
+;  V13 loc7         [V13    ] (  2,  8   )  simd12  ->  [rbp-0x90]  do-not-enreg[XS] addr-exposed ld-addr-op <System.Numerics.Vector3>
 ;# V14 OutArgs      [V14    ] (  1,  1   )  struct ( 0) [rsp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
 ;* V15 tmp1         [V15    ] (  0,  0   )   byref  ->  zero-ref   
-;  V16 tmp2         [V16,T15] (  2,  8   )   byref  ->  rcx        
-;  V17 tmp3         [V17,T14] (  3,  8   )     int  ->  rax        
+;  V16 tmp2         [V16,T14] (  2,  8   )   byref  ->  rcx        
+;  V17 tmp3         [V17,T13] (  3,  8   )     int  ->  rax        
 ;  V18 tmp4         [V18,T00] (  5, 40   )   byref  ->  rdi         "Inlining Arg"
 ;* V19 tmp5         [V19    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V20 tmp6         [V20    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V21 tmp7         [V21    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V22 tmp8         [V22    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;  V23 tmp9         [V23,T01] (  5, 40   )   byref  ->  rdi         "Inlining Arg"
 ;* V24 tmp10        [V24    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V25 tmp11        [V25    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V26 tmp12        [V26    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V27 tmp13        [V27    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V28 tmp14        [V28    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V29 tmp15        [V29    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V30 tmp16        [V30    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V31 tmp17        [V31    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
-;  V32 tmp18        [V32,T02] (  4, 32   )   byref  ->  rdi         "Inlining Arg"
+;* V32 tmp18        [V32    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V33 tmp19        [V33    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V34 tmp20        [V34    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V35 tmp21        [V35    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V36 tmp22        [V36    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
-;  V37 tmp23        [V37,T19] (  4, 32   )  simd12  ->  mm0         "Inlining Arg" <System.Numerics.Vector3>
-;  V38 tmp24        [V38,T03] (  4, 32   )   byref  ->  r10         "Inlining Arg"
+;  V37 tmp23        [V37,T16] (  4, 32   )  simd12  ->  mm0         "Inlining Arg" <System.Numerics.Vector3>
+;  V38 tmp24        [V38,T02] (  4, 32   )   byref  ->  r10         "Inlining Arg"
 ;* V39 tmp25        [V39    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V40 tmp26        [V40    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V41 tmp27        [V41    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
 ;* V42 tmp28        [V42    ] (  0,  0   )   byref  ->  zero-ref    "Inlining Arg"
-;  V43 tmp29        [V43,T20] (  2,  8   )   float  ->  mm0         "field V09.X (fldOffset=0x0)" P-INDEP
-;  V44 tmp30        [V44,T21] (  2,  8   )   float  ->  mm1         "field V09.Y (fldOffset=0x4)" P-INDEP
-;  V45 tmp31        [V45,T22] (  2,  8   )   float  ->  mm2         "field V09.Z (fldOffset=0x8)" P-INDEP
-;  V46 tmp32        [V46,T23] (  2,  8   )   float  ->  mm3         "field V10.X (fldOffset=0x0)" P-INDEP
-;  V47 tmp33        [V47,T24] (  2,  8   )   float  ->  mm4         "field V10.Y (fldOffset=0x4)" P-INDEP
-;  V48 tmp34        [V48,T25] (  2,  8   )   float  ->  mm5         "field V10.Z (fldOffset=0x8)" P-INDEP
-;  V49 cse0         [V49,T06] (  5, 20   )    long  ->  [rbp-0x78]  spill-single-def "CSE #02: aggressive"
-;  V50 cse1         [V50,T08] (  4, 16   )    long  ->  [rbp-0x80]  spill-single-def "CSE #01: aggressive"
-;  V51 rat0         [V51,T17] (  5, 40   )  simd12  ->  [rbp-0x90]  do-not-enreg[SF] "Spilled local for field list" <System.Numerics.Vector3>
-;  V52 rat1         [V52,T18] (  5, 40   )  simd12  ->  [rbp-0xA0]  do-not-enreg[SF] "Spilled local for field list" <System.Numerics.Vector3>
+;  V43 cse0         [V43,T05] (  5, 20   )    long  ->  [rbp-0x98]  spill-single-def "CSE #02: aggressive"
+;  V44 cse1         [V44,T07] (  4, 16   )    long  ->  [rbp-0xA0]  spill-single-def "CSE #01: aggressive"
 ;
 ; Lcl frame size = 136
 
 G_M10737_IG01:
        push     rbp
        push     r15
        push     r14
        push     r13
        push     r12
        push     rbx
        sub      rsp, 136
        lea      rbp, [rsp+0xB0]
        mov      bword ptr [rbp-0xA8], r9
        mov      rbx, rdi
        mov      r15, rsi
        mov      r14, rdx
        mov      r13, rcx
        mov      r12, r8
 						;; size=47 bbWeight=1 PerfScore 9.00
 G_M10737_IG02:
        xor      r8d, r8d
        jmp      SHORT G_M10737_IG05
 						;; size=5 bbWeight=1 PerfScore 2.25
 G_M10737_IG03:
        mov      eax, -1
 						;; size=5 bbWeight=2 PerfScore 0.50
 G_M10737_IG04:
        mov      dword ptr [rcx], eax
-       vmovss   xmm0, dword ptr [rbp-0x54]
-       mov      r9, qword ptr [rbp-0x80]
+       vmovss   xmm0, dword ptr [rbp-0x74]
+       mov      r9, qword ptr [rbp-0xA0]
        vmovss   dword ptr [r12+4*r9], xmm0
-       vmovaps  xmm0, xmmword ptr [rbp-0x70]
+       vmovaps  xmm0, xmmword ptr [rbp-0x90]
        mov      rax, bword ptr [rbp-0xA8]
        add      r10, rax
        vmovss   dword ptr [r10], xmm0
        vextractps dword ptr [r10+0x20], xmm0, 1
        vextractps dword ptr [r10+0x40], xmm0, 2
        mov      r8d, dword ptr [rbp-0x2C]
        inc      r8d
        mov      bword ptr [rbp-0xA8], rax
-						;; size=65 bbWeight=4 PerfScore 74.00
+						;; size=70 bbWeight=4 PerfScore 74.00
 G_M10737_IG05:
        cmp      r8d, dword ptr [rbx+0x08]
        jge      G_M10737_IG08
 						;; size=10 bbWeight=8 PerfScore 24.00
 G_M10737_IG06:
        mov      dword ptr [rbp-0x2C], r8d
        movsxd   r9, r8d
-       mov      qword ptr [rbp-0x80], r9
+       mov      qword ptr [rbp-0xA0], r9
        lea      r10, [4*r9]
-       mov      qword ptr [rbp-0x78], r10
+       mov      qword ptr [rbp-0x98], r10
        lea      rdi, bword ptr [r15+r10]
        vmovss   xmm0, dword ptr [rdi]
        vmovss   dword ptr [rbp-0x40], xmm0
        vmovss   xmm0, dword ptr [rdi+0x20]
        vmovss   dword ptr [rbp-0x3C], xmm0
        vmovss   xmm0, dword ptr [rdi+0x40]
        vmovss   dword ptr [rbp-0x38], xmm0
        add      rdi, 96
        vmovss   xmm0, dword ptr [rdi]
        vmovss   dword ptr [rbp-0x50], xmm0
        vmovss   xmm0, dword ptr [rdi+0x20]
        vmovss   dword ptr [rbp-0x4C], xmm0
        vmovss   xmm0, dword ptr [rdi+0x40]
        vmovss   dword ptr [rbp-0x48], xmm0
        vmovss   xmm0, dword ptr [rdi+0x60]
        vmovss   dword ptr [rbp-0x44], xmm0
        lea      rdi, bword ptr [r14+r10]
-       vmovss   xmm0, dword ptr [rdi]
-       vmovss   xmm1, dword ptr [rdi+0x20]
-       vmovss   xmm2, dword ptr [rdi+0x40]
-       add      rdi, 96
-       vmovss   xmm3, dword ptr [rdi]
-       vmovss   xmm4, dword ptr [rdi+0x20]
-       vmovss   xmm5, dword ptr [rdi+0x40]
+       vmovaps  xmm0, xmmword ptr [rbp-0x60]
+       vinsertps xmm0, xmm0, dword ptr [rdi], 0
+       vinsertps xmm0, xmm0, dword ptr [rdi+0x20], 16
+       vinsertps xmm0, xmm0, dword ptr [rdi+0x40], 32
+       vmovaps  xmmword ptr [rbp-0x60], xmm0
+       vmovaps  xmm0, xmmword ptr [rbp-0x70]
+       vinsertps xmm0, xmm0, dword ptr [rdi+0x60], 0
+       vinsertps xmm0, xmm0, dword ptr [rdi+0x80], 16
+       vinsertps xmm0, xmm0, dword ptr [rdi+0xA0], 32
+       vmovaps  xmmword ptr [rbp-0x70], xmm0
        mov      rdi, r9
        shl      rdi, 6
        add      rdi, qword ptr [rbx]
-       vmovss   dword ptr [rbp-0x90], xmm0
-       vmovss   dword ptr [rbp-0x8C], xmm1
-       vmovss   dword ptr [rbp-0x88], xmm2
-       vmovsd   xmm0, qword ptr [rbp-0x90]
-       vmovss   xmm1, dword ptr [rbp-0x88]
-       vmovss   dword ptr [rbp-0xA0], xmm3
-       vmovss   dword ptr [rbp-0x9C], xmm4
-       vmovss   dword ptr [rbp-0x98], xmm5
-       vmovsd   xmm2, qword ptr [rbp-0xA0]
-       vmovss   xmm3, dword ptr [rbp-0x98]
+       vmovsd   xmm0, qword ptr [rbp-0x60]
+       vmovss   xmm1, dword ptr [rbp-0x58]
+       vmovsd   xmm2, qword ptr [rbp-0x70]
+       vmovss   xmm3, dword ptr [rbp-0x68]
        lea      rsi, [rbp-0x50]
-       lea      rdx, [rbp-0x54]
-       lea      rcx, [rbp-0x70]
+       lea      rdx, [rbp-0x74]
+       lea      rcx, [rbp-0x90]
        mov      r11, 0xD1FFAB1E      ; code for BepuPhysics.Collidables.ConvexHull:RayTest(byref,System.Numerics.Vector3,System.Numerics.Vector3,byref,byref):bool:this
        call     [r11]BepuPhysics.Collidables.ConvexHull:RayTest(byref,System.Numerics.Vector3,System.Numerics.Vector3,byref,byref):bool:this
-       mov      r10, qword ptr [rbp-0x78]
+       mov      r10, qword ptr [rbp-0x98]
        lea      rcx, bword ptr [r10+r13]
        test     eax, eax
        jne      G_M10737_IG03
-						;; size=256 bbWeight=4 PerfScore 302.00
+						;; size=249 bbWeight=4 PerfScore 293.00
 G_M10737_IG07:
        xor      eax, eax
        jmp      G_M10737_IG04
 						;; size=7 bbWeight=2 PerfScore 4.50
 G_M10737_IG08:
        add      rsp, 136
        pop      rbx
        pop      r12
        pop      r13
        pop      r14
        pop      r15
        pop      rbp
        ret      
 						;; size=18 bbWeight=1 PerfScore 4.25
 
-; Total bytes of code 413, prolog size 25, PerfScore 420.50, instruction count 93, allocated bytes for code 413 (MethodHash=1031d60e) for method BepuPhysics.Collidables.ConvexHullWide:RayTest(byref,byref,byref,byref,byref):this (FullOpts)
+; Total bytes of code 411, prolog size 25, PerfScore 411.50, instruction count 90, allocated bytes for code 411 (MethodHash=1031d60e) for method BepuPhysics.Collidables.ConvexHullWide:RayTest(byref,byref,byref,byref,byref):this (FullOpts)
 ; ============================================================

Larger list of diffs: https://gist.github.com/MihuBot/7c9e0c0b04098b0400ae7e5b0297413f

[MihuBot]

@tannergooding