OpC_50 5F

5x Extended Addressing

If either of the register nibbles are odd for a 5x instruction, then extended addressing modes will be used for the instruction. The src and dest registers are obtained by stripping out the low bit of their nibbles. Note that this is still very much WIP and needs to be verified on hardware.

• Left Register odd, Right Register even - dest <- src op literal
• Left Register even, Right Register odd - dest <- src op (direct)
• Left Register odd, Right Register odd - dest <- index(src) op dest

Note that subtraction, division and XFR vary from the register to register variants. Examples are given in the table below.

Opcode	Operation	High nibble (src)	Low nibble (dest)	Meaning
51	SUB	Even	Odd	dest <- direct - src
51	SUB	Odd	Odd	dest <- index(src) - dest
55	XFR	Odd	Even	dest <- #literal
78	DIV	Even	Odd	dest <- src / direct
78	DIV	Odd	Odd	dest <- dest / index(src)