Add HBM support to mem_tg sample #3149
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
pcolberg
force-pushed
the
pcolberg/mem_tg_offset
branch
2 times, most recently
from
faf0b15 to
029f6e5
Compare
Pull Request Test Coverage Report for Build 12918090684Details
💛 - Coveralls |
Initialize the read/write start address to zero by default. Signed-off-by: Peter Colberg <[email protected]>
Add a function version_code() to combine major and minor version into a single code for comparison to, e.g., guard version-dependent features. Signed-off-by: Peter Colberg <[email protected]>
Add High Bandwidth Memory (HBM) support to the memory traffic generator (mem_tg) sample used to exercise and test available memory channels, which currently supports DDR memory only. For DDR, each memory channel accesses an independent memory bank, each starting from offset 0. For HBM, each memory channel has access to the entire memory space and must therefore access memory from different locations when reading or writing on multiple channels simultaneously to avoid collisions. For details on the HBM memory architecture, refer to the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide. Link: https://cdrdv2-public.intel.com/780779/ug-768844-780779.pdf Signed-off-by: Peter Colberg <[email protected]>
pcolberg
force-pushed
the
pcolberg/mem_tg_offset
branch
from
8861ad8 to
3f19f8a
Compare
michael-adler
approved these changes
Jan 22, 2025
Contributor
Author
|
Relevant debug output on Agilex 7 M-Series FPGA: |
Contributor
Author
|
Relevant debug output on N6001 FPGA with OFS 2024.2 FIM: Relevant debug output on N6001 FPGA with OFS 2024.3 FIM: |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Add High Bandwidth Memory (HBM) support to the memory traffic generator (mem_tg) sample used to exercise and test available memory channels, which currently supports DDR memory only. For DDR, each memory channel accesses an independent memory bank, each starting from offset 0.
For HBM, each memory channel has access to the entire memory space and must therefore access memory from different locations when reading or writing on multiple channels simultaneously to avoid collisions.
For details on the HBM memory architecture, refer to the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.
Link: https://cdrdv2-public.intel.com/780779/ug-768844-780779.pdf
Cc: @nanditha-intel @nahidhassan-intel @mdeckar1