Update SEC_BOOT_CFG5 register size to 32 bits

[ayodejiige]

No description provided.

[Copilot]

Pull Request Overview

This PR updates the SEC_BOOT_CFG5 register definition to use 32 bits instead of 16 bits, aligning the implementation with the correct hardware specification.

• Updated register size from 16 bits to 32 bits in both JSON configuration and generated Rust code
• Modified internal storage from 2-byte to 4-byte array to accommodate the larger size
• Updated all related type conversions and constants to maintain consistency

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated no comments.

File	Description
libs/imxrt-rom/src/registers/device.rs	Updated Rust struct implementation to use 4-byte array and 32-bit size constant
libs/imxrt-rom/registers.json	Changed register size specification from 16 to 32 bits

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[Wassasin]

This particular register is 16 bits however. Probably the method to write OTP fuses has an issue instead.

[Wassasin]

The problem is that for writing the register I have used chunks_exact, even though some registers are not a full OTP word large.

ec-slimloader/libs/imxrt-rom/src/registers.rs

Lines 114 to 119 in 76d6f5c

	for (i, chunk) in data.chunks_exact(4).enumerate() {
	// Safety: we have chunks of exactly 4 bytes, hence the conversion to [u8; 4] is safe.
	let word = u32::from_le_bytes(unsafe { chunk.try_into().unwrap_unchecked() });
	self.otp.write_fuse(address + i as u32, word, self.mode_locked)?;
	}

[Wassasin]

Fixed in #26. You can close this PR.