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Implement mffscdrn[i] and move mffs* to decodetree #65

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Implement mffscdrn[i] and move mffs* to decodetree #65

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d309abb
target/ppc: Fix insn32.decode style issues
vcoracolombo Jan 14, 2022
7bfecc5
target/ppc: Move mffs[.] to decodetree
vcoracolombo Jan 19, 2022
7869f4f
target/ppc: Move mffsl to decodetree
vcoracolombo Mar 10, 2022
04b99c6
target/ppc: Move mffsce to decodetree
vcoracolombo Mar 10, 2022
c66e338
target/ppc: Move mffscrn[i] to decodetree
vcoracolombo Mar 10, 2022
9ed4c5c
target/ppc: Implement mffscdrn[i] instructions
vcoracolombo Mar 10, 2022
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49 changes: 37 additions & 12 deletions target/ppc/insn32.decode
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Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,11 @@
#

&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
@D ...... rt:5 ra:5 si:s16 &D

&D_bf bf l:bool ra imm
@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
@D_bfs ...... bf:3 . l:1 ra:5 imm:s16 &D_bf
@D_bfu ...... bf:3 . l:1 ra:5 imm:16 &D_bf

%dq_si 4:s12 !function=times_16
%dq_rtp 22:4 !function=times_2
Expand All @@ -35,7 +35,7 @@
@DQ_TSXP ...... ..... ra:5 ............ .... &D si=%dq_si rt=%rt_tsxp

%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si

%ds_rtp 22:4 !function=times_2
@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
Expand All @@ -46,10 +46,10 @@

&DX rt d
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d

&VA vrt vra vrb rc
@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA

&VC vrt vra vrb rc:bool
@VC ...... vrt:5 vra:5 vrb:5 rc:1 .......... &VC
Expand All @@ -58,7 +58,7 @@
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN

&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX

&VX_bf bf vra vrb
@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
Expand All @@ -73,13 +73,13 @@
@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc

&VX_uim4 vrt uim vrb
@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4

&VX_tb vrt vrb
@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb
@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb

&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@X ...... rt:5 ra:5 rb:5 .......... . &X

&X_rc rt ra rb rc:bool
@X_rc ...... rt:5 ra:5 rb:5 .......... rc:1 &X_rc
Expand All @@ -91,6 +91,15 @@

@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp

&X_t rt
@X_t ...... rt:5 ..... ..... .......... . &X_t

&X_tb rt rb
@X_tb ...... rt:5 ..... rb:5 .......... . &X_tb

&X_t_rc rt rc:bool
@X_t_rc ...... rt:5 ..... ..... .......... rc:1 &X_t_rc

&X_tb_rc rt rb rc:bool
@X_tb_rc ...... rt:5 ..... rb:5 .......... rc:1 &X_tb_rc

Expand All @@ -101,7 +110,7 @@
@X_t_bp_rc ...... rt:5 ..... ....0 .......... rc:1 &X_tb_rc rb=%x_frbp

&X_bi rt bi
@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
@X_bi ...... rt:5 bi:5 ..... .......... . &X_bi

&X_bf bf ra rb
@X_bf ...... bf:3 .. ra:5 rb:5 .......... . &X_bf
Expand All @@ -116,7 +125,13 @@
@X_bf_uim_bp ...... bf:3 . uim:6 ....0 .......... . &X_bf_uim rb=%x_frbp

&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
@X_bfl ...... bf:3 . l:1 ra:5 rb:5 .......... . &X_bfl

&X_imm2 rt imm
@X_imm2 ...... rt:5 ..... ... imm:2 .......... . &X_imm2

&X_imm3 rt imm
@X_imm3 ...... rt:5 ..... .. imm:3 .......... . &X_imm3

%x_xt 0:1 21:5
&X_imm5 xt imm:uint8_t vrb
Expand Down Expand Up @@ -312,6 +327,16 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi

### Move To/From FPSCR

MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3

### Decimal Floating-Point Arithmetic Instructions

DADD 111011 ..... ..... ..... 0000000010 . @X_rc
Expand Down
3 changes: 0 additions & 3 deletions target/ppc/internal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -157,9 +157,6 @@ EXTRACT_HELPER(FPL, 25, 1);
EXTRACT_HELPER(FPFLM, 17, 8);
EXTRACT_HELPER(FPW, 16, 1);

/* mffscrni */
EXTRACT_HELPER(RM, 11, 2);

/* addpcis */
EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
#if defined(TARGET_PPC64)
Expand Down
168 changes: 78 additions & 90 deletions target/ppc/translate/fp-impl.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -589,141 +589,129 @@ static void gen_mcrfs(DisasContext *ctx)
tcg_temp_free_i64(tnew_fpscr);
}

/* mffs */
static void gen_mffs(DisasContext *ctx)
static void do_mffsc(int rt, TCGv_i64 t1, uint64_t set_mask,
uint64_t clear_mask, uint32_t fpscr_mask)
{
TCGv_i64 t0;
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
t0 = tcg_temp_new_i64();
TCGv_i64 fpscr;

fpscr = tcg_temp_new_i64();

gen_reset_fpstatus();
tcg_gen_extu_tl_i64(t0, cpu_fpscr);
set_fpr(rD(ctx->opcode), t0);
if (unlikely(Rc(ctx->opcode))) {
gen_set_cr1_from_fpscr(ctx);
tcg_gen_extu_tl_i64(fpscr, cpu_fpscr);
tcg_gen_andi_i64(fpscr, fpscr, set_mask);
set_fpr(rt, fpscr);

if (fpscr_mask) {
tcg_gen_andi_i64(fpscr, fpscr, clear_mask);
tcg_gen_or_i64(fpscr, fpscr, t1);
gen_helper_store_fpscr(cpu_env, fpscr, tcg_constant_i32(fpscr_mask));
}
tcg_temp_free_i64(t0);

tcg_temp_free_i64(fpscr);
}

/* mffsl */
static void gen_mffsl(DisasContext *ctx)
static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a)
{
TCGv_i64 t0;
REQUIRE_FPU(ctx);

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return gen_mffs(ctx);
do_mffsc(a->rt, tcg_constant_i64(0), 0xFFFFFFFFFFFFFFFFULL, 0, 0);
if (a->rc) {
gen_set_cr1_from_fpscr(ctx);
}

if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
t0 = tcg_temp_new_i64();
gen_reset_fpstatus();
tcg_gen_extu_tl_i64(t0, cpu_fpscr);
/* Mask everything except mode, status, and enables. */
tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
set_fpr(rD(ctx->opcode), t0);
tcg_temp_free_i64(t0);
return true;
}

/* mffsce */
static void gen_mffsce(DisasContext *ctx)
static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
{
TCGv_i64 t0;
TCGv_i32 mask;
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return gen_mffs(ctx);
}
do_mffsc(a->rt, tcg_constant_i64(0),
FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN, 0, 0);

if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}

t0 = tcg_temp_new_i64();
return true;
}

gen_reset_fpstatus();
tcg_gen_extu_tl_i64(t0, cpu_fpscr);
set_fpr(rD(ctx->opcode), t0);
static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a)
{
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);

/* Clear exception enable bits in the FPSCR. */
tcg_gen_andi_i64(t0, t0, ~FP_ENABLES);
mask = tcg_const_i32(0x0003);
gen_helper_store_fpscr(cpu_env, t0, mask);
do_mffsc(a->rt, tcg_constant_i64(0), 0xFFFFFFFFFFFFFFFFULL,
~FP_ENABLES, 0x0003);

tcg_temp_free_i32(mask);
tcg_temp_free_i64(t0);
return true;
}

static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i32 mask = tcg_const_i32(0x0001);
TCGv_i64 t1;

gen_reset_fpstatus();
tcg_gen_extu_tl_i64(t0, cpu_fpscr);
tcg_gen_andi_i64(t0, t0, FP_DRN | FP_ENABLES | FP_RN);
set_fpr(rD(ctx->opcode), t0);
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);

/* Mask FPSCR value to clear RN. */
tcg_gen_andi_i64(t0, t0, ~FP_RN);
t1 = tcg_temp_new_i64();
get_fpr(t1, a->rb);
tcg_gen_andi_i64(t1, t1, FP_RN);

/* Merge RN into FPSCR value. */
tcg_gen_or_i64(t0, t0, t1);
do_mffsc(a->rt, t1, FP_DRN | FP_ENABLES | FP_NI | FP_RN, ~FP_RN, 0x0001);

gen_helper_store_fpscr(cpu_env, t0, mask);
tcg_temp_free_i64(t1);

tcg_temp_free_i32(mask);
tcg_temp_free_i64(t0);
return true;
}

/* mffscrn */
static void gen_mffscrn(DisasContext *ctx)
static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a)
{
TCGv_i64 t1;

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return gen_mffs(ctx);
}

if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);

t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
/* Mask FRB to get just RN. */
tcg_gen_andi_i64(t1, t1, FP_RN);
tcg_gen_movi_i64(t1, a->imm);

gen_helper_mffscrn(ctx, t1);
do_mffsc(a->rt, t1, FP_DRN | FP_ENABLES | FP_NI | FP_RN, ~FP_RN, 0x0001);

tcg_temp_free_i64(t1);

return true;
}

/* mffscrni */
static void gen_mffscrni(DisasContext *ctx)
static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a)
{
TCGv_i64 t1;

if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return gen_mffs(ctx);
}
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);

if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
t1 = tcg_temp_new_i64();
get_fpr(t1, a->rb);
tcg_gen_andi_i64(t1, t1, FP_DRN);

do_mffsc(a->rt, t1, FP_DRN | FP_ENABLES | FP_NI | FP_RN, ~FP_DRN, 0x0100);

tcg_temp_free_i64(t1);

return true;
}

static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a)
{
TCGv_i64 t1;

t1 = tcg_const_i64((uint64_t)RM(ctx->opcode));
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);

t1 = tcg_temp_new_i64();
tcg_gen_movi_i64(t1, (uint64_t)a->imm << FPSCR_DRN0);

gen_helper_mffscrn(ctx, t1);
do_mffsc(a->rt, t1, FP_DRN | FP_ENABLES | FP_NI | FP_RN, ~FP_DRN, 0x0100);

tcg_temp_free_i64(t1);

return true;
}

/* mtfsb0 */
Expand Down
9 changes: 0 additions & 9 deletions target/ppc/translate/fp-ops.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -75,15 +75,6 @@ GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,
PPC_NONE),
GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT,
PPC_NONE),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
Expand Down