Add more consistancy tests

Pradeep2004 · Apr 21, 2020 · 056bf63 · 056bf63
1 parent b389878
commit 056bf63
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Showing 5 changed files with 442 additions and 302 deletions.
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -488,7 +488,9 @@ object VexRiscvSmpClusterTest extends App{
   }
 }
 
-
+// echo "echo 10000 | dhrystone >> log" > test
+// time sh test &
+// top -b -n 1
 object VexRiscvSmpClusterOpenSbi extends App{
   import spinal.core.sim._
 

diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -236,7 +236,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
             if(withLrSc) insert(MEMORY_FENCE_BACK) setWhen(input(MEMORY_LRSC))
             if(withAmo)  insert(MEMORY_FENCE_BACK) setWhen(input(MEMORY_AMO))
           }
-          when(input(INSTRUCTION)(25)) { //RL but a bit pessimistic as could be MEMORY_FENCE_BACK when the memory op isn't a read
+          when(input(INSTRUCTION)(25)) { //RL but a bit pessimistic as it could be MEMORY_FENCE_BACK when the memory op isn't a read
             if(withLrSc) insert(MEMORY_FENCE_FRONT) setWhen(input(MEMORY_LRSC))
             if(withAmo)  insert(MEMORY_FENCE_FRONT) setWhen(input(MEMORY_AMO))
           }