Riscv software model now implement interrupt priority accordingly to r…

…iscv-software-src/riscv-isa-sim@496c59d#diff-a38d447c5232bd448697af4c6c8adb1a changes
Pradeep2004 · Apr 21, 2019 · 14efe6f · 14efe6f
1 parent d7ca153
commit 14efe6f
Showing 1 changed file with 13 additions and 9 deletions.
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
@@ -637,15 +637,19 @@ class RiscvGolden {
 			masked = getIp().raw & mideleg & -sEnabled & ie.raw & 0x333;
 
 		if (masked) {
-			if (masked & (MIP_MEIP | MIP_SEIP))
-				masked &= (MIP_MEIP | MIP_SEIP);
-			// software interrupts have next-highest priority
-			else if (masked & (MIP_MSIP | MIP_SSIP))
-				masked &= (MIP_MSIP | MIP_SSIP);
-			// timer interrupts have next-highest priority
-			else if (masked & (MIP_MTIP | MIP_STIP))
-				masked &= (MIP_MTIP | MIP_STIP);
-			else
+			if (masked & MIP_MEIP)
+				masked &= MIP_MEIP;
+			else if (masked & MIP_MSIP)
+				masked &= MIP_MSIP;
+			else if (masked & MIP_MTIP)
+				masked &= MIP_MTIP;
+			else if (masked & MIP_SEIP)
+                masked &= MIP_SEIP;
+            else if (masked & MIP_SSIP)
+                masked &= MIP_SSIP;
+            else if (masked & MIP_STIP)
+                masked &= MIP_STIP;
+            else
 			  fail();
 		}