Merge remote-tracking branch 'origin/master' into linux

# Conflicts:
#	src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
#	src/test/cpp/regression/main.cpp

.gitignore

@@ -1,6 +1,7 @@
 *.class
 *.log
 *.bak
+.*.swp
 
 # sbt specific
 .cache/
@@ -48,4 +49,4 @@ obj_dir
 simWorkspace/
 tmp/
 /archive.tar.gz
-*.out32
+*.out32

README.md

@@ -127,7 +127,7 @@ Note that recently, the capability to remove the Fetch/Memory/WriteBack stage wa
 On Ubuntu 14 :
 
 ```sh
-# JAVA JDK 8. Do not try with JDK >= 9
+# JAVA JDK 8
 sudo add-apt-repository -y ppa:openjdk-r/ppa
 sudo apt-get update
 sudo apt-get install openjdk-8-jdk -y
@@ -337,16 +337,16 @@ Here are some timing and area measurements of the Murax SoC:
 
 ```
 Murax interlocked stages (0.45 DMIPS/Mhz, 8 bits GPIO) ->
-  Artix 7    -> 299 Mhz 984 LUT 1186 FF 
+  Artix 7    -> 299 Mhz 984 LUT 1186 FF
   Cyclone V  -> 175 Mhz 710 ALMs
-  Cyclone IV -> 137 Mhz 1,436 LUT 1,193 FF 
+  Cyclone IV -> 137 Mhz 1,436 LUT 1,193 FF
   iCE40      -> 48 Mhz 2337 LC (icestorm)
   iCE40Ultra -> 20 Mhz 2337 LC (icestorm)
 
 MuraxFast bypassed stages (0.65 DMIPS/Mhz, 8 bits GPIO) ->
-  Artix 7    -> 294 Mhz 1128 LUT 1219 FF 
+  Artix 7    -> 294 Mhz 1128 LUT 1219 FF
   Cyclone V  -> 165 Mhz 840 ALMs
-  Cyclone IV -> 141 Mhz 1,680 LUT 1,227 FF 
+  Cyclone IV -> 141 Mhz 1,680 LUT 1,227 FF
   iCE40      -> 48 Mhz 2702 LC (icestorm)
   iCE40Ultra -> 22 Mhz 2702 LC (icestorm)
 ```
@@ -653,18 +653,18 @@ This chapter describes plugins currently implemented.
 This plugin implement the CPU frontend (instruction fetch) via a very simple and neutral memory interface going outside the CPU.
 
 | Parameters | type | description |
-| ------ | ----------- | ------ | 
-| catchAccessFault | Boolean | If an the read response specify an read error and this parameter is true, it will generate an CPU exception trap |
-| resetVector | BigInt | Address of the program counter after the reset |
-| cmdForkOnSecondStage | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. |
-| cmdForkPersistence  | Boolean | If this parameter is false, then request on the iBus can disappear/change before their completion. Which reduce area but isn't safe/supported by many arbitration/slaves. If you set this parameter to true, then the iBus cmd will stay until they are completed.
-| compressedGen | Boolean | Enable RVC support |
-| busLatencyMin | Int | Specify the minimal latency between the iBus.cmd and iBus.rsp, which will add the corresponding number of stages into the frontend to keep the IPC to 1.|
-| injectorStage | Boolean | Add a stage between the frontend and the decode stage of the CPU to improve FMax. (busLatencyMin + injectorStage) should be at least two. | 
-| prediction | BranchPrediction | Can be set to NONE/STATIC/DYNAMIC/DYNAMIC_TARGET to specify the branch predictor implementation, see bellow for more descriptions |
-| historyRamSizeLog2 | Int | Specify the number of entries in the direct mapped prediction cache of DYNAMIC/DYNAMIC_TARGET implementation. 2 pow historyRamSizeLog2 entries |
-
-Here is the SimpleBus interface definition
+| ------ | ----------- | ------ |
+| catchAccessFault | Boolean | When true, an instruction read response with read error asserted results in a CPU exception trap. |
+| resetVector | BigInt | Address of the program counter after the reset. |
+| cmdForkOnSecondStage | Boolean | When false, branches immediately update the program counter. This minimizes branch penalties but might reduce FMax because the instruction bus address signal is a combinatorial path. When true, this combinatorial path is removed and the program counter is updated one cycle after a branch is detected. While FMax may improve, an additional branch penalty will be incurred as well. |
+| cmdForkPersistence  | Boolean | When false, requests on the iBus can disappear/change before they are acknowledged. This reduces area but isn't safe/supported by many arbitration/slaves. When true, once initiated, iBus requests will stay until they are acknowledged. |
+| compressedGen | Boolean | Enable RISC-V compressed instruction (RVC) support. |
+| busLatencyMin | Int | Specifies the minimal latency between the iBus.cmd and iBus.rsp. A corresponding number of stages are added to the frontend to keep the IPC to 1.|
+| injectorStage | Boolean | When true, a stage between the frontend and the decode stage of the CPU is added to improve FMax. (busLatencyMin + injectorStage) should be at least two. |
+| prediction | BranchPrediction | Can be set to NONE/STATIC/DYNAMIC/DYNAMIC_TARGET to specify the branch predictor implementation. See below for more details. |
+| historyRamSizeLog2 | Int | Specify the number of entries in the direct mapped prediction cache of DYNAMIC/DYNAMIC_TARGET implementation. 2 pow historyRamSizeLog2 entries. |
+
+Here is the SimpleBus interface definition:
 
 ```scala
 case class IBusSimpleCmd() extends Bundle{
@@ -695,52 +695,54 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
 
 Setting cmdForkPersistence and cmdForkOnSecondStage improves iBus cmd timings.
 
-Note that bridges are implemented to convert this interface into AXI4 and Avalon
+The iBusSimplePlugin includes bridges to convert from the IBusSimpleBus to AXI4, Avalon, and Wishbone interfaces.
 
-The jump interface implemented by this plugin allow all other plugin to request jumps. The stage argument specify from which stage the jump is asked, which will allow the PcManagerSimplePlugin plugin to manage priorities between jump requests.
+This plugin implements a jump interface that allows all other plugins to issue a jump:
 
 ```scala
 trait JumpService{
   def createJumpInterface(stage : Stage) : Flow[UInt]
 }
 ```
 
+The stage argument specifies the stage from which the jump is asked. This allows the PcManagerSimplePlugin plugin to manage priorities between jump requests from
+diffent stages.
 
 #### IBusCachedPlugin
 
 Simple and light multi-way instruction cache.
 
 | Parameters | type | description |
 | ------ | ----------- | ------ |
-| cacheSize  | Int | Total storage capacity of the cache |
-| bytePerLine  | Int | Number of bytes per cache line  |
-| wayCount  | Int | Number of cache ways |
-| twoCycleRam  | Boolean | Check the tags values in the decode stage instead of the fetch stage to relax timings |
-| asyncTagMemory  | Boolean | Read the cache tags in a asyncronus manner instead of syncronous one |
-| addressWidth  | Int | Address width, should be 32 |
-| cpuDataWidth  | Int | Cpu data width, should be 32 |
-| memDataWidth  | Int | Memory data width, could potentialy be something else than 32, but only 32 is currently tested |
-| catchIllegalAccess  | Boolean  | Catch when a memory access is done on non valid memory address (MMU) |
-| catchAccessFault  | Boolean | Catch when the memeory bus is responding with an error  |
-| catchMemoryTranslationMiss  | Boolean  |  Catch when the MMU miss a TLB |
-| resetVector | BigInt | Address of the program counter after the reset |
-| relaxedPcCalculation | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. |
-| compressedGen | Boolean | Enable RVC support |
-| prediction | BranchPrediction | Can be set to NONE/STATIC/DYNAMIC/DYNAMIC_TARGET to specify the branch predictor implementation, see bellow for more descriptions |
+| resetVector | BigInt | Address of the program counter after the reset. |
+| relaxedPcCalculation | Boolean | When false, branches immediately update the program counter. This minimizes branch penalties but might reduce FMax because the instruction bus address signal is a combinatorial path. When true, this combinatorial path is removed and the program counter is updated one cycle after a branch is detected. While FMax may improve, an additional branch penalty will be incurred as well. |
+| prediction | BranchPrediction | Can be set to NONE/STATIC/DYNAMIC/DYNAMIC_TARGET to specify the branch predictor implementation. See below for more details. |
 | historyRamSizeLog2 | Int | Specify the number of entries in the direct mapped prediction cache of DYNAMIC/DYNAMIC_TARGET implementation. 2 pow historyRamSizeLog2 entries |
-
-Note: If you enable the twoCycleRam option and if wayCount is bigger than one, then the register file plugin should be configured to read the regFile in a asynchronous manner.
+| compressedGen | Boolean | Enable RISC-V compressed instruction (RVC) support. |
+| config.cacheSize  | Int | Total storage capacity of the cache in bytes. |
+| config.bytePerLine  | Int | Number of bytes per cache line  |
+| config.wayCount  | Int | Number of cache ways |
+| config.twoCycleRam  | Boolean | Check the tags values in the decode stage instead of the fetch stage to relax timings |
+| config.asyncTagMemory  | Boolean | Read the cache tags in an asynchronous manner instead of syncronous one |
+| config.addressWidth  | Int | CPU address width. Should be 32 |
+| config.cpuDataWidth  | Int | CPU data width. Should be 32 |
+| config.memDataWidth  | Int | Memory data width. Could potentialy be something else than 32, but only 32 is currently tested |
+| config.catchIllegalAccess  | Boolean  | Catch when a memory access is done on non-valid memory address (MMU) |
+| config.catchAccessFault  | Boolean | Catch when the memeory bus is responding with an error  |
+| config.catchMemoryTranslationMiss  | Boolean  |  Catch when the MMU miss a TLB |
+
+Note: If you enable the twoCycleRam option and if wayCount is bigger than one, then the register file plugin should be configured to read the regFile in an asynchronous manner.
 
 #### DecoderSimplePlugin
 
 This plugin provides instruction decoding capabilities to others plugins.
 
-For instance, for a given instruction, the pipeline hazard plugin needs to know if it uses the register file source 1/2 in order stall the pipeline until the hazard is gone.
+For instance, for a given instruction, the pipeline hazard plugin needs to know if it uses the register file source 1/2 in order to stall the pipeline until the hazard is gone.
 To provide this kind of information, each plugin which implements an instruction documents this kind of information to the DecoderSimplePlugin plugin.
 
 | Parameters | type | description |
 | ------ | ----------- | ------ |
-| catchIllegalInstruction | Boolean | If set to true, instruction which have no decoding specification will generate a trap exception  |
+| catchIllegalInstruction | Boolean | When true, instructions that don't match a decoding specification will generate a trap exception  |
 
 Here is a usage example :
 
@@ -752,11 +754,11 @@ Here is a usage example :
 
       //Decoding specification when the 'key' pattern is recognized in the instruction
       List(
-        IS_SIMD_ADD              -> True,
-        REGFILE_WRITE_VALID      -> True, //Enable the register file write
+        IS_SIMD_ADD              -> True, //Inform the pipeline that the current instruction is a SIMD_ADD instruction
+        REGFILE_WRITE_VALID      -> True, //Notify the hazard management unit that this instruction writes to the register file
         BYPASSABLE_EXECUTE_STAGE -> True, //Notify the hazard management unit that the instruction result is already accessible in the EXECUTE stage (Bypass ready)
         BYPASSABLE_MEMORY_STAGE  -> True, //Same as above but for the memory stage
-        RS1_USE                  -> True, //Notify the hazard management unit that this instruction use the RS1 value
+        RS1_USE                  -> True, //Notify the hazard management unit that this instruction uses the RS1 value
         RS2_USE                  -> True  //Same than above but for RS2.
       )
     )

scripts/Murax/iCE40-hx8k_breakout_board/README.md

@@ -2,7 +2,8 @@ This example is for the
 [Lattice iCE40HX-8K Breakout Board](http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx).
 
 An image of this board is shown below;
-![img/iCE40HX8K-breakout-revA.png]
+
+![`iCE40HX8K breakout revA`](img/iCE40HX8K-breakout-revA.png)
 
 This board can be purchased for ~$USD 49 directly from Lattice and is supported
 by the IceStorm
@@ -20,7 +21,8 @@ mode. This requires removing jumper `J7` and putting the pair of jumpers on
 This is shown in **Figure 5** of the
 [iCE40HX-8K Breakout Board User Guide](http://www.latticesemi.com/view_document?document_id=50373).
 which is also reproduced below;
-![img/cram-programming-config.png]
+
+![CRAM Programming Config](img/cram-programming-config.png)
 
 Once your board is ready, you should follow the setup instructions at the
 [top level](../../../README.md).

scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md

@@ -2,7 +2,8 @@ This example is for the
 [Lattice iCE40HX-8K Breakout Board](http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx).
 
 An image of this board is shown below;
-![img/iCE40HX8K-breakout-revA.png]
+
+![`iCE40HX8K breakout revA`](img/iCE40HX8K-breakout-revA.png)
 
 This board can be purchased for ~$USD 49 directly from Lattice and is supported
 by the IceStorm
@@ -20,7 +21,8 @@ mode. This requires removing jumper `J7` and putting the pair of jumpers on
 This is shown in **Figure 5** of the
 [iCE40HX-8K Breakout Board User Guide](http://www.latticesemi.com/view_document?document_id=50373).
 which is also reproduced below;
-![img/cram-programming-config.png]
+
+![CRAM Programming Config](img/cram-programming-config.png)
 
 Once your board is ready, you should follow the setup instructions at the
 [top level](../../../README.md).

src/main/scala/vexriscv/demo/GenFullNoMmuNoCacheSimpleMul.scala

@@ -0,0 +1,63 @@
+package vexriscv.demo
+
+import vexriscv.plugin._
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
+import spinal.core._
+
+/**
+ * Created by spinalvm on 15.06.17.
+ */
+object GenFullNoMmuNoCacheSimpleMul extends App{
+  def cpu() = new VexRiscv(
+    config = VexRiscvConfig(
+      plugins = List(
+        new IBusSimplePlugin(
+          resetVector = 0x80000000l,
+          cmdForkOnSecondStage = false,
+          cmdForkPersistence = false,
+          prediction = STATIC,
+          catchAccessFault = false,
+          compressedGen = false
+        ),
+        new DBusSimplePlugin(
+          catchAddressMisaligned = false,
+          catchAccessFault = false
+        ),
+        new DecoderSimplePlugin(
+          catchIllegalInstruction = true
+        ),
+        new RegFilePlugin(
+          regFileReadyKind = plugin.SYNC,
+          zeroBoot = false
+        ),
+        new IntAluPlugin,
+        new SrcPlugin(
+          separatedAddSub = false,
+          executeInsertion = true
+        ),
+        new FullBarrelShifterPlugin,
+        new HazardSimplePlugin(
+          bypassExecute           = true,
+          bypassMemory            = true,
+          bypassWriteBack         = true,
+          bypassWriteBackBuffer   = true,
+          pessimisticUseSrc       = false,
+          pessimisticWriteRegFile = false,
+          pessimisticAddressMatch = false
+        ),
+        new MulSimplePlugin,
+        new DivPlugin,
+        new CsrPlugin(CsrPluginConfig.small),
+        new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
+        new BranchPlugin(
+          earlyBranch = false,
+          catchAddressMisaligned = true
+        ),
+        new YamlPlugin("cpu0.yaml")
+      )
+    )
+  )
+
+  SpinalVerilog(cpu())
+}

src/main/scala/vexriscv/demo/GenMicroNoCsr.scala

@@ -0,0 +1,61 @@
+package vexriscv.demo
+
+import vexriscv.plugin._
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
+import spinal.core._
+
+/**
+ * Created by spinalvm on 15.06.17.
+ */
+object GenMicroNoCsr extends App{
+  def cpu() = new VexRiscv(
+    config = VexRiscvConfig(
+      withMemoryStage = false,
+      withWriteBackStage = false,
+      plugins = List(
+        new IBusSimplePlugin(
+          resetVector = 0x80000000l,
+          cmdForkOnSecondStage = false,
+          cmdForkPersistence = false,
+          prediction = NONE,
+          catchAccessFault = false,
+          compressedGen = false
+        ),
+        new DBusSimplePlugin(
+          catchAddressMisaligned = false,
+          catchAccessFault = false,
+          earlyInjection = false
+        ),
+        new DecoderSimplePlugin(
+          catchIllegalInstruction = false
+        ),
+        new RegFilePlugin(
+          regFileReadyKind = plugin.SYNC,
+          zeroBoot = false,
+          writeRfInMemoryStage = false
+        ),
+        new IntAluPlugin,
+        new SrcPlugin(
+          separatedAddSub = false,
+          executeInsertion = false
+        ),
+        new LightShifterPlugin,
+        new HazardSimplePlugin(
+          bypassExecute           = false,
+          bypassMemory            = false,
+          bypassWriteBack         = false,
+          bypassWriteBackBuffer   = false,
+          pessimisticUseSrc       = false,
+          pessimisticWriteRegFile = false,
+          pessimisticAddressMatch = false
+        ),
+        new BranchPlugin(
+          earlyBranch = true,
+          catchAddressMisaligned = false
+        ),
+        new YamlPlugin("cpu0.yaml")
+      )
+    )
+  )
+  SpinalConfig(mergeAsyncProcess = false).generateVerilog(cpu())
+}

src/main/scala/vexriscv/plugin/BranchPlugin.scala

@@ -55,6 +55,7 @@ class BranchPlugin(earlyBranch : Boolean,
                    fenceiGenAsAJump : Boolean = false,
                    fenceiGenAsANop : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{
 
+
   def catchAddressMisalignedForReal = catchAddressMisaligned && !pipeline(RVC_GEN)
   lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory
 
@@ -88,6 +89,8 @@ class BranchPlugin(earlyBranch : Boolean,
     import pipeline.config._
     import IntAluPlugin._
 
+    assert(earlyBranch || withMemoryStage, "earlyBranch must be true when memory stage is disabled!")
+
     val bActions = List[(Stageable[_ <: BaseType],Any)](
       SRC1_CTRL         -> Src1CtrlEnum.RS,
       SRC2_CTRL         -> Src2CtrlEnum.RS,
@@ -265,7 +268,7 @@ class BranchPlugin(earlyBranch : Boolean,
         default{
           branch_src1 := input(PC)
           branch_src2 := ((input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
-          when(input(PREDICTION_HAD_BRANCHED) && ! missAlignedTarget){
+          when(input(PREDICTION_HAD_BRANCHED)){ //Assume the predictor never predict missaligned stuff, this avoid the need to know if the instruction should branch or not
             branch_src2 := (if(pipeline(RVC_GEN)) Mux(input(IS_RVC), B(2), B(4)) else B(4)).asUInt.resized
           }
         }
@@ -375,4 +378,4 @@ class BranchPlugin(earlyBranch : Boolean,
       }
     }
   }
-}
+}

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -65,6 +65,12 @@ object DBusSimpleBus{
     useBTE = true,
     useCTI = true
   )
+
+  def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
+    addressWidth = 32,
+    dataWidth = 32
+  )
+
 }
 
 case class DBusSimpleBus() extends Bundle with IMasterSlave{
@@ -180,7 +186,8 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
   }
 
   def toPipelinedMemoryBus() : PipelinedMemoryBus = {
-    val bus = PipelinedMemoryBus(32,32)
+    val pipelinedMemoryBusConfig = DBusSimpleBus.getPipelinedMemoryBusConfig()
+    val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
     bus.cmd.valid := cmd.valid
     bus.cmd.write := cmd.wr
     bus.cmd.address := cmd.address.resized