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fpga clock name changed to Clk_C16 and Clk_C21 #33

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24 changes: 12 additions & 12 deletions adc_ad7476_if/rtl/AL4S3B_FPGA_Top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -114,11 +114,11 @@ wire RST_IP;

wire WB_CLK ; // Selected FPGA Clock

wire Sys_Clk0 ; // Selected FPGA Clock
wire Sys_Clk0_Rst ; // Selected FPGA Reset
wire Clk_C16 ; // Selected FPGA Clock
wire Clk_C16_Rst ; // Selected FPGA Reset

wire Sys_Clk1 ; // Selected FPGA Clock
wire Sys_Clk1_Rst ; // Selected FPGA Reset
wire Clk_C21 ; // Selected FPGA Clock
wire Clk_C21_Rst ; // Selected FPGA Reset

// Wishbone Bus Signals
//
Expand Down Expand Up @@ -170,11 +170,11 @@ assign gnd_o = 1'b0;
// Determine the FPGA reset
//
// Note: Reset the FPGA IP on either the AHB or clock domain reset signals.
gclkbuff u_gclkbuff_reset ( .A(Sys_Clk0_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Sys_Clk0 ) , .Z(WB_CLK ) );
gclkbuff u_gclkbuff_reset ( .A(Clk_C16_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Clk_C16 ) , .Z(WB_CLK ) );

assign RST_IP = Sys_Clk1_Rst;
assign CLK_IP = Sys_Clk1;
assign RST_IP = Clk_C21_Rst;
assign CLK_IP = Clk_C21;

//------Instantiate Modules------------
//
Expand Down Expand Up @@ -306,10 +306,10 @@ qlal4s3b_cell_macro u_qlal4s3b_cell_macro
//
// FB Clocks
//
.Sys_Clk0 ( Sys_Clk0 ), // output
.Sys_Clk0_Rst ( Sys_Clk0_Rst ), // output
.Sys_Clk1 ( Sys_Clk1 ), // output
.Sys_Clk1_Rst ( Sys_Clk1_Rst ), // output
.Clk_C16 ( Clk_C16 ), // output
.Clk_C16_Rst ( Clk_C16_Rst ), // output
.Clk_C21 ( Clk_C21 ), // output
.Clk_C21_Rst ( Clk_C21_Rst ), // output
//
// Packet FIFO
//
Expand Down
26 changes: 13 additions & 13 deletions projects/S3_FLL_I2S/rtl/AL4S3B_FPGA_Top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -35,11 +35,11 @@ wire RST_IP ;

wire WB_CLK ; // Selected FPGA Clock

wire Sys_Clk0 ; // Selected FPGA Clock
wire Sys_Clk0_Rst ; // Selected FPGA Reset
wire Clk_C16 ; // Selected FPGA Clock
wire Clk_C16_Rst ; // Selected FPGA Reset

wire Sys_Clk1 ; // Selected FPGA Clock
wire Sys_Clk1_Rst ; // Selected FPGA Reset
wire Clk_C21 ; // Selected FPGA Clock
wire Clk_C21_Rst ; // Selected FPGA Reset

// Wishbone Bus Signals
wire [16:0] WBs_ADR ; // Wishbone Address Bus
Expand Down Expand Up @@ -78,12 +78,12 @@ wire dbg_bitclks ;
// Determine the FPGA reset
//
// Note: Reset the FPGA IP on either the AHB or clock domain reset signals.
gclkbuff u_gclkbuff_reset ( .A(Sys_Clk0_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock0 ( .A(Sys_Clk0 ) , .Z(WB_CLK ) );
gclkbuff u_gclkbuff_reset ( .A(Clk_C16_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock0 ( .A(Clk_C16 ) , .Z(WB_CLK ) );

gclkbuff u_gclkbuff_clock1 ( .A(Sys_Clk1 ) , .Z(bitclk_local ) );
gclkbuff u_gclkbuff_clock1 ( .A(Clk_C21 ) , .Z(bitclk_local ) );

assign RST_IP = Sys_Clk1_Rst;
assign RST_IP = Clk_C21_Rst;
assign CLK_IP = bitclk_local;

gclkbuff u_gclkbuff_bitclkm ( .A(bitclk_master) , .Z(bitclk_master_gclk) );
Expand Down Expand Up @@ -152,10 +152,10 @@ qlal4s3b_cell_macro u_qlal4s3b_cell_macro (
.FB_Busy ( 1'b0 ), // input

// FB Clocks
.Sys_Clk0 ( Sys_Clk0 ), // output
.Sys_Clk0_Rst ( Sys_Clk0_Rst ), // output
.Sys_Clk1 ( Sys_Clk1 ), // output
.Sys_Clk1_Rst ( Sys_Clk1_Rst ), // output
.Clk_C16 ( Clk_C16 ), // output
.Clk_C16_Rst ( Clk_C16_Rst ), // output
.Clk_C21 ( Clk_C21 ), // output
.Clk_C21_Rst ( Clk_C21_Rst ), // output

// Packet FIFO
.Sys_PKfb_Clk ( 1'b0 ), // input
Expand Down Expand Up @@ -222,7 +222,7 @@ assign dbg_int_slowdown = Interrupt_slowdown ;
//assign dbg_bitclkm = bitclk_master_gclk ;
assign dbg_bitclkm = bitclk_master ;
//assign dbg_bitclks = bitclk_local ;
assign dbg_bitclks = Sys_Clk1 ;
assign dbg_bitclks = Clk_C21 ;

endmodule

24 changes: 12 additions & 12 deletions projects/S3_FPGA_2xUART/rtl/AL4S3B_FPGA_Top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -95,11 +95,11 @@ wire RST_IP;

wire WB_CLK ; // Selected FPGA Clock

wire Sys_Clk0 ; // Selected FPGA Clock
wire Sys_Clk0_Rst ; // Selected FPGA Reset
wire Clk_C16 ; // Selected FPGA Clock
wire Clk_C16_Rst ; // Selected FPGA Reset

wire Sys_Clk1 ; // Selected FPGA Clock
wire Sys_Clk1_Rst ; // Selected FPGA Reset
wire Clk_C21 ; // Selected FPGA Clock
wire Clk_C21_Rst ; // Selected FPGA Reset

// Wishbone Bus Signals
//
Expand Down Expand Up @@ -138,11 +138,11 @@ assign gnd_o = 1'b0;
// Determine the FPGA reset
//
// Note: Reset the FPGA IP on either the AHB or clock domain reset signals.
gclkbuff u_gclkbuff_reset ( .A(Sys_Clk0_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Sys_Clk0 ) , .Z(WB_CLK ) );
gclkbuff u_gclkbuff_reset ( .A(Clk_C16_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Clk_C16 ) , .Z(WB_CLK ) );

assign RST_IP = Sys_Clk1_Rst;
assign CLK_IP = Sys_Clk1;
assign RST_IP = Clk_C21_Rst;
assign CLK_IP = Clk_C21;

//------Instantiate Modules------------
//
Expand Down Expand Up @@ -257,10 +257,10 @@ qlal4s3b_cell_macro u_qlal4s3b_cell_macro
//
// FB Clocks
//
.Sys_Clk0 ( Sys_Clk0 ), // output
.Sys_Clk0_Rst ( Sys_Clk0_Rst ), // output
.Sys_Clk1 ( Sys_Clk1 ), // output
.Sys_Clk1_Rst ( Sys_Clk1_Rst ), // output
.Clk_C16 ( Clk_C16 ), // output
.Clk_C16_Rst ( Clk_C16_Rst ), // output
.Clk_C21 ( Clk_C21 ), // output
.Clk_C21_Rst ( Clk_C21_Rst ), // output
//
// Packet FIFO
//
Expand Down
24 changes: 12 additions & 12 deletions projects/S3_FPGA_UART/rtl/AL4S3B_FPGA_Top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -86,11 +86,11 @@ wire RST_IP;

wire WB_CLK ; // Selected FPGA Clock

wire Sys_Clk0 ; // Selected FPGA Clock
wire Sys_Clk0_Rst ; // Selected FPGA Reset
wire Clk_C16 ; // Selected FPGA Clock
wire Clk_C16_Rst ; // Selected FPGA Reset

wire Sys_Clk1 ; // Selected FPGA Clock
wire Sys_Clk1_Rst ; // Selected FPGA Reset
wire Clk_C21 ; // Selected FPGA Clock
wire Clk_C21_Rst ; // Selected FPGA Reset

// Wishbone Bus Signals
//
Expand Down Expand Up @@ -122,11 +122,11 @@ assign gnd_o = 1'b0;
// Determine the FPGA reset
//
// Note: Reset the FPGA IP on either the AHB or clock domain reset signals.
gclkbuff u_gclkbuff_reset ( .A(Sys_Clk0_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Sys_Clk0 ) , .Z(WB_CLK ) );
gclkbuff u_gclkbuff_reset ( .A(Clk_C16_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Clk_C16 ) , .Z(WB_CLK ) );

assign RST_IP = Sys_Clk1_Rst;
assign CLK_IP = Sys_Clk1;
assign RST_IP = Clk_C21_Rst;
assign CLK_IP = Clk_C21;

//------Instantiate Modules------------
//
Expand Down Expand Up @@ -234,10 +234,10 @@ qlal4s3b_cell_macro u_qlal4s3b_cell_macro
//
// FB Clocks
//
.Sys_Clk0 ( Sys_Clk0 ), // output
.Sys_Clk0_Rst ( Sys_Clk0_Rst ), // output
.Sys_Clk1 ( Sys_Clk1 ), // output
.Sys_Clk1_Rst ( Sys_Clk1_Rst ), // output
.Clk_C16 ( Clk_C16 ), // output
.Clk_C16_Rst ( Clk_C16_Rst ), // output
.Clk_C21 ( Clk_C21 ), // output
.Clk_C21_Rst ( Clk_C21_Rst ), // output
//
// Packet FIFO
//
Expand Down
24 changes: 12 additions & 12 deletions projects/S3_FPGA_UART_GPIO/rtl/AL4S3B_FPGA_Top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -30,11 +30,11 @@ wire RST_IP ;

wire WB_CLK ; // Selected FPGA Clock

wire Sys_Clk0 ; // Selected FPGA Clock
wire Sys_Clk0_Rst ; // Selected FPGA Reset
wire Clk_C16 ; // Selected FPGA Clock
wire Clk_C16_Rst ; // Selected FPGA Reset

wire Sys_Clk1 ; // Selected FPGA Clock
wire Sys_Clk1_Rst ; // Selected FPGA Reset
wire Clk_C21 ; // Selected FPGA Clock
wire Clk_C21_Rst ; // Selected FPGA Reset

// Wishbone Bus Signals
wire [16:0] WBs_ADR ; // Wishbone Address Bus
Expand Down Expand Up @@ -65,11 +65,11 @@ wire [31:0] GPIO;
// Determine the FPGA reset
//
// Note: Reset the FPGA IP on either the AHB or clock domain reset signals.
gclkbuff u_gclkbuff_reset ( .A(Sys_Clk0_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Sys_Clk0 ) , .Z(WB_CLK ) );
gclkbuff u_gclkbuff_reset ( .A(Clk_C16_Rst | WB_RST) , .Z(WB_RST_FPGA) );
gclkbuff u_gclkbuff_clock ( .A(Clk_C16 ) , .Z(WB_CLK ) );

assign RST_IP = Sys_Clk1_Rst;
assign CLK_IP = Sys_Clk1;
assign RST_IP = Clk_C21_Rst;
assign CLK_IP = Clk_C21;

assign GPIO_io = GPIO[3:0];

Expand Down Expand Up @@ -134,10 +134,10 @@ qlal4s3b_cell_macro u_qlal4s3b_cell_macro (
.FB_Busy ( 1'b0 ), // input

// FB Clocks
.Sys_Clk0 ( Sys_Clk0 ), // output
.Sys_Clk0_Rst ( Sys_Clk0_Rst ), // output
.Sys_Clk1 ( Sys_Clk1 ), // output
.Sys_Clk1_Rst ( Sys_Clk1_Rst ), // output
.Clk_C16 ( Clk_C16 ), // output
.Clk_C16_Rst ( Clk_C16_Rst ), // output
.Clk_C21 ( Clk_C21 ), // output
.Clk_C21_Rst ( Clk_C21_Rst ), // output

// Packet FIFO
.Sys_PKfb_Clk ( 1'b0 ), // input
Expand Down