This repository contains our final project for the course "Computer Architecture" offered in Spring 2024. We were tasked with creating a non-pipelined processor that could run a sorting algorithm (we chose bubble sort), then pipeline said processor and implement proper forwarding and hazard detection such that the pipelined processor could run a sorting algorithm.
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"Task 1" contains a non-pipelined processor where bubble sort functions perfectly.
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"Task 2" contains a pipelined processor with a forwarding unit; however, the bubble sort does not function due to the lack of a hazard detection unit.
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"Task 3" contains a pipelined processor with a forwarding and hazard detection unit where bubble sort functions perfectly. This is the final version of the pipelined processor.
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"Project Report" contains our final report for the project detailing our process.
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"Bubble Sort Code" contains the assembly instructions we used to simulate bubble sort"
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"Bubble Sort Instructions (for Verilog)" contains the instructions that were given to the Verilog processor to simulate the assembly instructions.