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…RTERS The original AVX512 implementation used incorrect 4-argument macros that only shuffled within single registers. For proper row/column processing, AVX512 requires inter-register shuffles using: - SWAP_HALVES for row processing (BLAKE2_ROUND_1_AVX512) - SWAP_QUARTERS/UNSWAP_QUARTERS for column processing (BLAKE2_ROUND_2_AVX512) This matches the PHC reference implementation's approach and ensures correct hash output with -O3 -march=native optimizations. Part of the fix for commit c0e59cf 'Rinhash: add native CPU optimizations' which introduced buggy SIMD code for AVX2, SSSE3, and AVX512.
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Release v1.0.2
Overview
This release introduces significant performance improvements, enhanced CPU optimizations, and comprehensive testnet/regtest network parameter updates.
Key Features
🚀 Performance Improvements
⚡ Rinhash CPU Optimizations
🌐 Network Updates
Technical Changes
Modified Files (27 files, +2164/-113 lines):
src/crypto/argon2/with multiple SIMD variantssrc/chainparams.cppandsrc/chainparamsseeds.hsrc/qt/coincontroldialog.cppandsrc/qt/modaloverlay.cppconfigure.acandsrc/Makefile.amCommits
c0e59cfRinhash: add native CPU optimizations3bb8c83Speed up Qt sync and payment dialogsde08fd4Chainparams: new dns+ip seeds, complete new testnet+regtest params incl. genesisbc6f40bsequential blockfile read0757187TestNet chainparams + version update 1.0.2Version
Bumped to v1.0.2
Testing