Pacman in verilog. Can be run of a Nexys4 FPGA board.. Final project for EE354 at USC.
How certain aspects are implemented: The Pacman module takes in maze 2D register and checks for collision with wall. Outputs pacmanFill (if the current hCount and vCount is outputing the RGB of pacman)
Collision
The scoring module will detect if pacFill and pelletFill are invoked at the same time, or if pacFill and ghostFill is invoked at the same time. (ghostFill will be a OR of all the seperate ghostFills)
There will be a wire in the top module that is an OR of all the ghost collision outputs and acts as an input for Pacman to see if they collide or not
Pacman and pellet collision is accounted for by the scoring module
WIN signal is generated by the scoring module and taken as input by every module (including scoring module itself)
LOSE signal is generated by ghost and taken as input as every module (including ghost itself)
Each module takes in their own generated signal to make it such that all the state machines are synced up and no state machine is one clock ahead