[pull] master from YosysHQ:master #372
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Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
…r better interoperability with other synthesis tools and RTL languages
* Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks. And the style edits - they get automatically when I make sure to run clang-format10. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
* apicula: add support for magic sip pins * fix nullptr check * DDR fix by xiwang * WIP support for setting the iostd * add iostd
Signed-off-by: gatecat <[email protected]>
* convert nodes to pips * add plane info for node pips * a few multiplier router fixes * do not need node delay * add pip delays * cleanup * tried fixing clock router * add PLL delays * fix clock routing * Do not use actual pip delay, determine best by number of passed pips * optimize * proper parameter check * more multiplier fixes * another mult fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * another multiplier fix * log number of clock net users * Revert "Do not use actual pip delay, determine best by number of passed pips" This reverts commit c66e422. We want to guarantee minimum clock skew, so we need pip delay. * route clocks from source to sink * add time spent to route_clock * weakly-bind non-global clocks * clangformat * remove dead code * Require version 1.8 * change to assert * add revisits in clock router --------- Co-authored-by: Lofty <[email protected]>
* Check SER_CLK more * Use connectPorts * move rewire code * Move data structures * move placement decision for later * cleanups * find working layout * clangformat * Inverted input on ODDR * Fix some tests * Copy clocks for multi die * cleanup * reporting * bugfix * handle PLL special inputs * Fix user globals * Proper DDR per bank and cleanup * Add extra data for die regions and create them * Better forced_die implementation * Copy region to newly generated cells, and update when constrained * Update PLL error messages * Add TODO comment
Over time, it became clear that the special status of corner tiles is handled in other parts of the toolchain, and in the GW5A chip series, it began to interfere—in this series, IO can be located in the corners. So we move the only function (creating VCC and GND) to the extra function itself, and at the same time create a mechanism for explicitly specifying the location of these sources in Apicula when necessary. Signed-off-by: YRabbit <[email protected]>
In the new series of chips, the SemiDual Port primitive has one RESET pin instead of two in previous versions - RESETA and RESETB. Physically, the two pins are still there and both must be connected, with RESETA being constant. Signed-off-by: YRabbit <[email protected]>
If the chipdb is not found, the Setup() call throws, but GTest still calls TearDown, which then stumbles over the uninitialized pointer. This makes the tests fail without valgrind errors or segfaults at least.
…parated by a comma (#1571)
* rust: formatting cleanup * rust: explicitly mark as ISC license * rust: use std::ffi C types instead of libc dependency
In the GW5A series, the primitive SemiDual Port BSRAM cannot function when the width of any of the ports is 32/36 bits - it is necessary to divide one block into two identical ones, each of which will be responsible for 16 bits. Here, we perform such a division and, in addition, ensure that the new cells resulting from the division undergo the same packing procedure as the original ones. Naturally, with some reservations (the AUX attribute is responsible for this) - in the case of SP, when service elements are added, it makes sense to do this immediately for 32-bit SP and only then divide. Also, SDPs are currently being corrected for cases where both ports are ‘problematic’, but it may happen that one port is 32 and the other is, say, 1/2/4/8/16. This has been left for the future. Signed-off-by: YRabbit <[email protected]>
* Use QtPropertyBrowser for Qt5/6 * Fix cmake for python-console for consistency * Make GUI compile for both Qt5 and Qt6 * Fix crash on init with Wayland on Qt6 * Cleanup * disable deprecation warnings for now * Relaxed cmake check for initial Qt6 test
* gatemate: support multiple clock distribution strategies * error out on non supported cases * Implement full use strategy * Address review comments
* gatemate: document clock distribution strategies * gatemate: rename option to strategy
Co-authored-by: OpenProgger <[email protected]>
* remove copy of googletest from 3rdparty * Add googletest as submodule * Use googletest v1.17.0 * Update main CMakeLists.txt
Paired with YosysHQ/yosys@6535995 now that we may receive unattached OBUFs, we ignore them. Signed-off-by: YRabbit <[email protected]>
* gatemate: Use GATEMATE_DIE attribute to select placement die * add DIE parameter in CCF * add penalty delay when crossing between dies * Add predictDelay
* himbaechel: add uarch specific options parsing * fix tests * add reference to additional help * review comments addressed * cleanup and unify other uarch * Adressed PR comments
Signed-off-by: gatecat <[email protected]>
Since ctx->getArchArgs() no longer returns architecture-specific arguments, we read the args field directly. Signed-off-by: YRabbit <[email protected]>
* Cleanup Context API * Remove exit to prvent crash
* gatemate: handle default parameters for IO This is probably a VHDL specific issue. In VHDL, there is no black-box. Primitive instantiations are done using VHDL component instantiations and the component must have been declared with all its ports and parameters (generic). Currently the components are translated from cells_sim.v and cells_bb.v If a user doesn't override a parameter, the default value is used instead. As a consequence, nextpnr can have 'UNDEFINED' for DRIVER or SLEW parameters of CC_IOBUF. I think this is a main difference with verilog, where unspecified parameters do not appear. With this change, the UNPLACED value of PIN_NAME and UNDEFINED value of DRIVE are simply ignored. * gatemate/pack_io.cc: also handle UNDEFINED for id_SLEW
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