AXI4

AMBA/AXI/v4/AXI4.unconstrained.vhdl

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+-- EMACS settings: -*-	tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:         Rob Gaddi
+--                  Patrick Lehmann
+--
+-- Package:         VHDL-2019 AXI4 interface descriptions
+--
+-- Description:
+-- -------------------------------------
+-- This package 
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2020 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+use     work.Axi4Common.all;
+
+
+package Axi4 is
+	type Axi4_Address_Interface is record
+		-- Handshake signals
+		Valid     : std_ulogic;
+		Ready     : std_ulogic;
+
+		-- Payload signals
+		ID        : 
+		Address   : Address_Type;
+		Len       : Length_Type;
+		Size      : Size_Type;
+		Burst     : Burst_Type;
+		Lock      : Lock_Type;
+		QoS       : QualityOfService_Type;
+		Region    : Region_Type;
+		Cache     : Cache_Type;
+		Protect   : Protect_Type;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_WriteData_Interface is record
+		-- Handshake signals
+		Valid     : std_ulogic;
+		Ready     : std_ulogic;
+
+		-- Payload signals
+		Data      : Data_Type;
+		Strobe    : Strobe_Type;
+		Last      : std_ulogic;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_WriteResponse_Interface is record
+		-- Handshake signals
+		Valid     : std_ulogic;
+		Ready     : std_ulogic;
+
+		-- Payload signals
+		ID        : 
+		Response  : Response_Type;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_ReadData_Interface is record
+		-- Handshake signals
+		Valid   : std_ulogic;
+		Ready   : std_ulogic;
+
+		-- Payload signals
+		ID        : 
+		Response  : Response_Type;
+
+		Data      : Data_Type;
+		Last      : std_ulogic;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_Interface is record
+		WriteAddress   : Axi4_Address_Interface;
+		WriteData      : Axi4_WriteData_Interface;
+		WriteResponse  : Axi4_WriteResponse_Interface;
+		ReadAddress    : Axi4_Address_Interface;
+		ReadData       : Axi4_ReadData_Interface;
+	end record;
+
+	-- All lower-level views are defined from the driver's point of view.
+	view Axi4_Address_MasterView of Axi4_Address_Interface is
+		-- Handshake signals
+		Valid     : out;
+		Ready     : in;
+
+		-- Payload signals
+		Address   : out;
+		Cache     : out;
+		Protect   : out;
+	end view;
+	alias Axi4_Address_SlaveView is Axi4_Address_MasterView'converse;
+
+	view Axi4_WriteData_MasterView of Axi4_WriteData_Interface is
+		-- Handshake signals
+		Valid     : out;
+		Ready     : in;
+
+		-- Payload signals
+		Data      : out;
+		Strobe    : out;
+	end view;
+	alias Axi4_WriteData_SlaveView is Axi4_WriteData_MasterView'converse;
+
+	view Axi4_WriteResponse_MasterView of Axi4_WriteResponse_Interface is
+		-- Handshake signals
+		Valid     : in;
+		Ready     : out;
+
+		-- Payload signals
+		Response  : in;
+	end view;
+	alias Axi4_WriteResponse_SlaveView is Axi4_WriteResponse_MasterView'converse;
+
+	view Axi4_ReadData_MasterView of Axi4_ReadData_Interface is
+		-- Handshake signals
+		Valid     : in;
+		Ready     : out;
+
+		-- Payload signals
+		Data      : in;
+		Response  : in;
+	end view;
+	alias Axi4_ReadData_SlaveView is Axi4_ReadData_MasterView'converse;
+
+	view Axi4_MasterView of Axi4_Interface is
+		WriteAddress   : view Axi4_Address_MasterView;
+		WriteData      : view Axi4_WriteData_MasterView;
+		WriteResponse  : view Axi4_WriteResponse_MasterView;
+		ReadAddress    : view Axi4_Address_MasterView;
+		ReadData       : view Axi4_ReadData_MasterView;
+	end view;
+	alias Axi4_SlaveView is Axi4_MasterView'converse;
+end package;

AMBA/AXI/v4/AXI4Common.vhdl

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+-- EMACS settings: -*-	tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:         Patrick Lehmann
+--
+-- Package:         VHDL-2019 Common types in AXI4 interface descriptions
+--
+-- Description:
+-- -------------------------------------
+-- This package 
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2020 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+
+package Axi4Common is
+	-- Common to all AXI buses
+	subtype Data_Type     is std_ulogic_vector;
+	subtype User_Type     is std_ulogic_vector;
+
+	-- Unique to AXI-Stream
+	subtype Keep_Type     is std_ulogic_vector;
+
+	-- Unique to AXI-Lite
+	subtype Address_Type  is unresolved_unsigned;
+	subtype Strobe_Type   is std_ulogic_vector;
+
+
+	-- Unique to AXI
+	subtype ID_Type               is unresolved_unsigned;
+	subtype Region_Type           is std_ulogic_vector(3 downto 0);
+  subtype Cache_Type            is std_ulogic_vector(3 downto 0);
+  subtype QualityOfService_Type is std_ulogic_vector(3 downto 0);
+
+
+  subtype  Size_Type is unresolved_unsigned(2 downto 0);
+  constant AXI4_SIZE_1          : Size_Type := "000";
+  constant AXI4_SIZE_2          : Size_Type := "001";
+  constant AXI4_SIZE_4          : Size_Type := "010";
+  constant AXI4_SIZE_8          : Size_Type := "011";
+  constant AXI4_SIZE_16         : Size_Type := "100";
+  constant AXI4_SIZE_32         : Size_Type := "101";
+  constant AXI4_SIZE_64         : Size_Type := "110";
+  constant AXI4_SIZE_128        : Size_Type := "111";
+
+
+  subtype  Burst_Type is std_ulogic_vector(1 downto 0);
+  constant AXI4_BURST_FIXED     : Burst_Type := "00";
+  constant AXI4_BURST_INCR      : Burst_Type := "01";
+  constant AXI4_BURST_WRAP      : Burst_Type := "10";
+
+
+	subtype Response_Type is std_ulogic_vector(1 downto 0);
+	constant AXI4_RESPONSE_OKAY         : Response_Type := "00";
+	constant AXI4_RESPONSE_EX_OKAY      : Response_Type := "01";
+	constant AXI4_RESPONSE_SLAVE_ERROR  : Response_Type := "10";
+	constant AXI4_RESPONSE_DECODE_ERROR : Response_Type := "11";
+
+
+	subtype Protect_Type is std_ulogic_vector(2 downto 0);
+  -- Bit 0: 0 Unprivileged access   1 Privileged access
+  -- Bit 1: 0 Secure access         1 Non-secure access
+  -- Bit 2: 0 Data access           1 Instruction access
+  constant AXI4_PROTECT_INIT          : Protect_Type := "UUU"; 
+  constant AXI4_PROTECT_NONE          : Protect_Type := "000"; 	
+
+
+	type AXI4_System_Interface is record
+		Clock    : std_ulogic;
+		Reset_n  : std_ulogic;
+	end record;
+
+end package;

AMBA/AXI/v4/AXI4Lite.generic.vhdl

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+-- EMACS settings: -*-	tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:         Patrick Lehmann
+--
+-- Generic Package: Generic AXI4-Lite interface descriptions for pre-constraining
+--
+-- Description:
+-- -------------------------------------
+-- This package 
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2020 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+use work.Axi4Lite.all;
+
+
+package Axi4Lite_Generic is
+	generic (
+		constant ADDRESS_BITS : positive;
+		constant DATA_BITS    : positive;
+		constant STROBE_BITS  : positive := DATA_BITS / 8
+	);
+
+	subtype Axi4Lite_Address_SizedInterface is Axi4Lite_Address_Interface(
+		Address(ADDRESS_BITS - 1 downto 0)
+	);
+
+	subtype Axi4Lite_WriteData_SizedInterface is Axi4Lite_WriteData_Interface(
+		Data(DATA_BITS - 1 downto 0),
+		Strobe(STROBE_BITS - 1 downto 0)
+	);
+
+	subtype Axi4Lite_ReadData_SizedInterface is Axi4Lite_ReadData_Interface(
+		Data(DATA_BITS - 1 downto 0)
+	);
+
+	subtype Axi4Lite_SizedInterface is Axi4Lite_Interface(
+		WriteAddress(
+			Address(ADDRESS_BITS - 1 downto 0)
+		),
+		WriteData(
+			Data(DATA_BITS - 1 downto 0),
+			Strobe(STROBE_BITS - 1 downto 0)
+		),
+		ReadAddress(
+			Address(ADDRESS_BITS - 1 downto 0)
+		),
+		ReadData(
+			Data(DATA_BITS - 1 downto 0)
+		)
+	);
+end package;