Prepare first release candidate

.editorconfig

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+root = true
+
+[*]
+charset = utf-8
+# end_of_line = lf
+insert_final_newline = true
+trim_trailing_whitespace = true
+indent_style = tab
+indent_size = 2
+tab_width = 2
+
+
+[*.py]
+indent_style = tab
+indent_size = 2
+
+[*.{yml,yaml}]
+indent_style = space
+indent_size = 2
+
+[*.{json,ini}]
+indent_style = tab
+indent_size = 2
+
+[*.md]
+trim_trailing_whitespace = false
+
+[*.rst]
+indent_style = space
+indent_size = 3

.gitignore

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-/temp
+# Python cache and object files
+__pycache__/
+*.py[cod]
+
+# Sphinx documentation
+/doc/_build
+
+# PyCharm project
+/.idea/workspace.xml
+
+# Temperary generated outputs from scripts
+/temp

.readthedocs.yml

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+version: 2
+
+submodules:
+  include: []
+
+build:
+  image: latest
+
+python:
+  version: 3.8
+  install:
+    - requirements: doc/requirements.txt
+
+sphinx:
+  builder: html
+  configuration: doc/conf.py
+
+formats:
+  - pdf
+#  - htmlzip
+#  - epub

AMBA/AXI/v4/AXI4.unconstrained.vhdl

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+-- =============================================================================
+-- Authors:
+--   Rob Gaddi
+--   Patrick Lehmann
+--
+-- Package:
+--   VHDL-2019 AXI4 interface descriptions
+--
+-- Description:
+--   Undocumented
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2023 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+use     work.Axi4Common.all;
+
+
+package Axi4 is
+	type Axi4_Address_Interface is record
+		-- Handshake signals
+		Valid     : std_ulogic;
+		Ready     : std_ulogic;
+
+		-- Payload signals
+		ID        : ID_Type;
+		Address   : Address_Type;
+		Len       : Length_Type;
+		Size      : Size_Type;
+		Burst     : Burst_Type;
+		Lock      : Lock_Type;
+		QoS       : QualityOfService_Type;
+		Region    : Region_Type;
+		Cache     : Cache_Type;
+		Protect   : Protect_Type;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_WriteData_Interface is record
+		-- Handshake signals
+		Valid     : std_ulogic;
+		Ready     : std_ulogic;
+
+		-- Payload signals
+		Data      : Data_Type;
+		Strobe    : Strobe_Type;
+		Last      : std_ulogic;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_WriteResponse_Interface is record
+		-- Handshake signals
+		Valid     : std_ulogic;
+		Ready     : std_ulogic;
+
+		-- Payload signals
+		ID        : ID_Type;
+		Response  : Response_Type;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_ReadData_Interface is record
+		-- Handshake signals
+		Valid   : std_ulogic;
+		Ready   : std_ulogic;
+
+		-- Payload signals
+		ID        : ID_Type;
+		Response  : Response_Type;
+
+		Data      : Data_Type;
+		Last      : std_ulogic;
+
+		User      : User_Type;
+	end record;
+
+	type Axi4_Interface is record
+		WriteAddress   : Axi4_Address_Interface;
+		WriteData      : Axi4_WriteData_Interface;
+		WriteResponse  : Axi4_WriteResponse_Interface;
+		ReadAddress    : Axi4_Address_Interface;
+		ReadData       : Axi4_ReadData_Interface;
+	end record;
+
+	-- All lower-level views are defined from the driver's point of view.
+	view Axi4_Address_MasterView of Axi4_Address_Interface is
+		-- Handshake signals
+		Valid     : out;
+		Ready     : in;
+
+		-- Payload signals
+		ID        : out;
+		Address   : out;
+		Len       : out;
+		Size      : out;
+		Burst     : out;
+		Lock      : out;
+		QoS       : out;
+		Region    : out;
+		Cache     : out;
+		Protect   : out;
+		User      : out;
+	end view;
+	alias Axi4_Address_SlaveView is Axi4_Address_MasterView'converse;
+
+	view Axi4_WriteData_MasterView of Axi4_WriteData_Interface is
+		-- Handshake signals
+		Valid     : out;
+		Ready     : in;
+
+		-- Payload signals
+		Data      : out;
+		Strobe    : out;
+		Last      : out;
+		User      : out;
+	end view;
+	alias Axi4_WriteData_SlaveView is Axi4_WriteData_MasterView'converse;
+
+	view Axi4_WriteResponse_MasterView of Axi4_WriteResponse_Interface is
+		-- Handshake signals
+		Valid     : in;
+		Ready     : out;
+
+		-- Payload signals
+		ID        : in;
+		Response  : in;
+		User      : in;
+	end view;
+	alias Axi4_WriteResponse_SlaveView is Axi4_WriteResponse_MasterView'converse;
+
+	view Axi4_ReadData_MasterView of Axi4_ReadData_Interface is
+		-- Handshake signals
+		Valid     : in;
+		Ready     : out;
+
+		-- Payload signals
+		ID        : in;
+		Response  : in;
+		Data      : in;
+		Last      : in;
+		User      : in;
+	end view;
+	alias Axi4_ReadData_SlaveView is Axi4_ReadData_MasterView'converse;
+
+	view Axi4_MasterView of Axi4_Interface is
+		WriteAddress   : view Axi4_Address_MasterView;
+		WriteData      : view Axi4_WriteData_MasterView;
+		WriteResponse  : view Axi4_WriteResponse_MasterView;
+		ReadAddress    : view Axi4_Address_MasterView;
+		ReadData       : view Axi4_ReadData_MasterView;
+	end view;
+	alias Axi4_SlaveView is Axi4_MasterView'converse;
+
+end package;

AMBA/AXI/v4/AXI4Common.vhdl

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+-- =============================================================================
+-- Authors:
+--   Patrick Lehmann
+--
+-- Package:
+--   VHDL-2019 Common types in AXI4 interface descriptions
+--
+-- Description:
+--   Undocumented
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2023 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+
+package Axi4Common is
+	-- Common to all AXI buses
+	subtype Data_Type     is std_ulogic_vector;
+	subtype User_Type     is std_ulogic_vector;
+
+	-- Unique to AXI-Stream
+	subtype Keep_Type     is std_ulogic_vector;
+
+	-- Unique to AXI-Lite
+	subtype Address_Type  is unresolved_unsigned;
+	subtype Strobe_Type   is std_ulogic_vector;
+
+
+	-- Unique to AXI
+	subtype ID_Type               is unsigned;
+	subtype Length_Type           is unsigned(3 downto 0);
+	subtype Lock_Type             is std_ulogic_vector(3 downto 0);
+	subtype Region_Type           is std_ulogic_vector(3 downto 0);
+  subtype Cache_Type            is std_ulogic_vector(3 downto 0);
+  subtype QualityOfService_Type is std_ulogic_vector(3 downto 0);
+
+
+  subtype  Size_Type is unsigned(2 downto 0);
+  constant AXI4_SIZE_1          : Size_Type := "000";
+  constant AXI4_SIZE_2          : Size_Type := "001";
+  constant AXI4_SIZE_4          : Size_Type := "010";
+  constant AXI4_SIZE_8          : Size_Type := "011";
+  constant AXI4_SIZE_16         : Size_Type := "100";
+  constant AXI4_SIZE_32         : Size_Type := "101";
+  constant AXI4_SIZE_64         : Size_Type := "110";
+  constant AXI4_SIZE_128        : Size_Type := "111";
+
+
+  subtype  Burst_Type is std_ulogic_vector(1 downto 0);
+  constant AXI4_BURST_FIXED     : Burst_Type := "00";
+  constant AXI4_BURST_INCR      : Burst_Type := "01";
+  constant AXI4_BURST_WRAP      : Burst_Type := "10";
+
+
+	subtype Response_Type is std_ulogic_vector(1 downto 0);
+	constant AXI4_RESPONSE_OKAY         : Response_Type := "00";
+	constant AXI4_RESPONSE_EX_OKAY      : Response_Type := "01";
+	constant AXI4_RESPONSE_SLAVE_ERROR  : Response_Type := "10";
+	constant AXI4_RESPONSE_DECODE_ERROR : Response_Type := "11";
+
+
+	subtype Protect_Type is std_ulogic_vector(2 downto 0);
+  -- Bit 0: 0 Unprivileged access   1 Privileged access
+  -- Bit 1: 0 Secure access         1 Non-secure access
+  -- Bit 2: 0 Data access           1 Instruction access
+  constant AXI4_PROTECT_INIT          : Protect_Type := "UUU";
+  constant AXI4_PROTECT_NONE          : Protect_Type := "000";
+
+
+	type AXI4_System_Interface is record
+		Clock    : std_ulogic;
+		Reset_n  : std_ulogic;
+	end record;
+
+end package;