Updated AXI4Lite register testcase

tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl

@@ -0,0 +1,111 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:
+--                  Adrian Weiland (PLC2 Design GmbH)
+--
+-- Entity:          ReadWrite
+--
+-- Description:
+-- -------------------------------------
+-- Test-Case ReadWrite
+--
+-- License:
+-- =============================================================================
+-- Copyright 2025-2025 The PoC-Library Authors
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--        http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+architecture ReadWrite of AXI4Lite_Register_TestController is
+
+	signal TestDone   : integer_barrier := 1 ;
+	signal ConfigDone : integer_barrier := 1 ;
+
+	constant number : positive := 7;
+	constant TCID      : AlertLogIDType :=  NewID("TestCtrl");
+
+begin
+
+  ------------------------------------------------------------
+  -- ControlProc
+  --   Set up AlertLog and wait for end of test
+  ------------------------------------------------------------
+	ControlProc : process
+		constant ProcID  : AlertLogIDType := NewID("ControlProc", TCID);
+		constant TIMEOUT : time := 10 ms;
+	begin
+		-- Initialization of test
+		SetAlertLogName("AXI4Lite_Register_ReadWrite") ;
+		SetLogEnable(PASSED,                   FALSE);
+		SetLogEnable(INFO,                     FALSE);
+		SetLogEnable(osvvm.AlertLogPkg.DEBUG,  FALSE);
+		wait for 0 ns; wait for 0 ns;
+
+		TranscriptOpen;
+		SetTranscriptMirror(TRUE);
+		ClearAlerts;
+
+		WaitForBarrier(TestDone, TIMEOUT);
+		EndOfTestReports(ReportAll => TRUE, Timeout => now >= TIMEOUT);
+		std.env.finish;
+		wait;
+	end process ControlProc ;
+
+	ManagerProc : process
+
+		procedure WriteCheck (
+			RegName   : string;
+			addr      : AXIAddressType;
+			write_val : AXIDataType
+		) is
+			variable idx : integer;
+		begin
+			idx := get_index(RegName, CONF);
+			WriteCheck(AxiMasterTransRec, ReadPort, WritePort, idx, addr, write_val);
+		end procedure;
+
+	begin
+		nReset <= '1';
+
+		WaitForClock(AxiMasterTransRec, 2) ;
+
+		-- check writable registers
+		log("Verify all the registers");
+		WriteCheck("Reg3",   32x"08", 32x"02");
+		WriteCheck("Reg4_L", 32x"10", 32x"FF");
+		WriteCheck("Reg4_H", 32x"14", 32x"2A");
+
+		-- try to access reserved registers
+		log("Trying to write reserved registers");
+		WriteReserved(AxiMasterTransRec, 32x"0C");
+		WriteReserved(AxiMasterTransRec, 32x"18");
+		WriteReserved(AxiMasterTransRec, 32x"1C");
+		WriteReserved(AxiMasterTransRec, 32x"50");
+
+		WaitForClock(AxiMasterTransRec);
+	    WaitForBarrier(TestDone);
+		wait;
+
+	end process;
+
+end architecture;
+
+configuration AXI4Lite_Register_ReadWrite of AXI4Lite_Register_TestHarness is
+	for sim
+		for TestCtrl : AXI4Lite_Register_TestController
+			use entity work.AXI4Lite_Register_TestController(ReadWrite) ;
+		end for ;
+	end for;
+end configuration ;

tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl

@@ -5,6 +5,7 @@
 -- Authors:
 --                  Iqbal Asif (PLC2 Design GmbH)
 --                  Patrick Lehmann (PLC2 Design GmbH)
+--                  Adrian Weiland (PLC2 Design GmbH)
 --
 -- Entity:          AXI4Lite_Register_TestController
 --
@@ -29,46 +30,49 @@
 -- limitations under the License.
 -- =============================================================================
 
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.numeric_std_unsigned.all;
+library IEEE ;
+use     IEEE.std_logic_1164.all ;
+use     IEEE.numeric_std.all ;
+use     IEEE.numeric_std_unsigned.all ;
 
 library PoC;
-use PoC.utils.all;
-use PoC.vectors.all;
-use PoC.axi4lite.all;
+use     PoC.utils.all;
+use     PoC.vectors.all;
+use     PoC.axi4lite.all;
 
 library OSVVM;
 context OSVVM.OsvvmContext;
 
 library osvvm_common;
 context osvvm_common.OsvvmCommonContext;
 
-library OSVVM_AXI4;
+library OSVVM_AXI4 ;
 context OSVVM_AXI4.Axi4LiteContext;
 
+use     work.AXI4Lite_Register_pkg.all;
+
+
 entity AXI4Lite_Register_TestController is
 	generic (
-		CONFIG : T_AXI4_Register_Vector
+		CONF : T_AXI4_Register_Vector
 	);
 	port (
 		-- Global Signal Interface
-		Clock : in std_logic;
-		Reset : in std_logic;
+		Clk    : in    std_logic ;
+		nReset : out   std_logic ;
 
-		Irq : in std_logic;
+		Irq : in    std_logic;
 
-		ReadPort  : in T_SLVV(0 to CONFIG'Length - 1)(DATA_BITS - 1 downto 0);
-		WritePort : out T_SLVV(0 to CONFIG'Length - 1)(DATA_BITS - 1 downto 0) := (others => (others => '0'));
+		ReadPort  : in   T_SLVV(0 to CONF'Length - 1)(DATA_BITS-1 downto 0);
+		WritePort : out  T_SLVV(0 to CONF'Length - 1)(DATA_BITS-1 downto 0):= (others => (others => '0'));
 
 		-- Transaction Interfaces
-		AxiMasterTransRec : inout Axi4LiteMasterTransactionRecType
-	);
-	constant AXI_ADDR_WIDTH : integer := AxiMasterTransRec.Address'length;
-	constant AXI_DATA_WIDTH : integer := AxiMasterTransRec.DataToModel'length;
+		AxiMasterTransRec         : inout Axi4LiteMasterTransactionRecType
+	) ;
+	constant AXI_ADDR_WIDTH : integer := AxiMasterTransRec.Address'length ;
+	constant AXI_DATA_WIDTH : integer := AxiMasterTransRec.DataToModel'length ;
 
-	-- Not currently used in the Axi4Lite model - future use for Axi4Lite Burst Emulation modes
-	--  alias WriteBurstFifo is <<variable .TbAxi4.Master_1.WriteBurstFifo : osvvm.ScoreboardPkg_slv.ScoreboardPType>> ;
-	--  alias ReadBurstFifo  is <<variable .TbAxi4.Master_1.ReadBurstFifo  : osvvm.ScoreboardPkg_slv.ScoreboardPType>> ;
+-- Not currently used in the Axi4Lite model - future use for Axi4Lite Burst Emulation modes
+--  alias WriteBurstFifo is <<variable .TbAxi4.Master_1.WriteBurstFifo : osvvm.ScoreboardPkg_slv.ScoreboardPType>> ;
+--  alias ReadBurstFifo  is <<variable .TbAxi4.Master_1.ReadBurstFifo  : osvvm.ScoreboardPkg_slv.ScoreboardPType>> ;
 end entity;