AIE/Design/04_custome_platform_emu: Updating DEVICE NAME from ES to Prod

Co-authored-by: virata <[email protected]>
Xilinx · May 2, 2022 · 291e744 · 291e744
1 parent 978a2bd
commit 291e744
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diff --git a/...elopment/Design_Tutorials/04-custom-platform-emulation/pl_kernels/hdl/vhdl/polar_clip.vhd b/...elopment/Design_Tutorials/04-custom-platform-emulation/pl_kernels/hdl/vhdl/polar_clip.vhd
@@ -51,7 +51,7 @@ end;
 architecture behav of polar_clip is 
     attribute CORE_GENERATION_INFO : STRING;
     attribute CORE_GENERATION_INFO of behav : architecture is
-    "polar_clip_polar_clip,hls_ip_2020_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcvc1902-vsva2197-2MP-e-S-es1,HLS_INPUT_CLOCK=6.667000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.761750,HLS_SYN_LAT=18,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=1362,HLS_SYN_LUT=1450,HLS_VERSION=2020_2}";
+    "polar_clip_polar_clip,hls_ip_2020_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xcvc1902-vsva2197-2MP-e-S,HLS_INPUT_CLOCK=6.667000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.761750,HLS_SYN_LAT=18,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=1362,HLS_SYN_LUT=1450,HLS_VERSION=2020_2}";
     constant ap_const_logic_1 : STD_LOGIC := '1';
     constant ap_const_logic_0 : STD_LOGIC := '0';
     constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000001";

diff --git a/Developer_Contributed/01-Versal_Custom_Thin_Platform_Extensible_System/platform/hw/Makefile b/Developer_Contributed/01-Versal_Custom_Thin_Platform_Extensible_System/platform/hw/Makefile
@@ -45,7 +45,7 @@ CREATE_XSA_TCL := platform_xsa.tcl
 ifeq ($(DEVICE_NAME), xcvc1902-vsva2197-2MP-e-S)
   BOARD_LABEL:=vck190
   BOARD_VER:=3.0
-else ifeq ($(DEVICE_NAME), xcvc1902-vsva2197-2MP-e-S-es1)
+else ifeq ($(DEVICE_NAME), xcvc1902-vsva2197-2MP-e-S)
   BOARD_LABEL:=vck190_es
   BOARD_VER:=1.3
 endif