Add HDL DUC example #67
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| * 4 stages of FIR filter, with interpolation ratio of 2 in each stage and the overall interpolation ratio of 16. | ||
| * The first stage is a 64 tap square raised root cosine (SRRC) filter, and the next three stage filters are half-band (HB) interpolate by 2 FIR filter. | ||
| * 4 stages of FIR filter, with interpolation ratio of 2 in each stage and an overall interpolation ratio of 16. | ||
| * The first stage is a 64 tap square raised root cosine (SRRC) filter, and the next three stage filters are half-band (HB) interpolate-by-2 FIR filters. | ||
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| ## Example Model | ||
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we should say, one using kernels with buffer interfaces and the other using kernels with stream interfaces.
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In the latency section, it says "The latency of the AI Engine design can be viewed in the Vitis Analyzer." I think this should be Model Composer and not Vitis Analyzer.
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I find the information in the Resource utilization section pretty light weight.
We should briefly say how to open the Vitis Analyzer from the Hub block.
We touch on kernels runtime ratios and suggest that the design is not ideal. But I am not sure why we stop there instead of changing runtime ratios and showing how we can optimize the design. Any opportunity to show how to optimize designs is useful to the end user. This is example presents a great opportunity.
This section should be redone to be a lot more informative.
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