4 - Full accl support

custom_hls/accl/CMakeLists.txt

@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.9)
+project(node_model)
+
+set(CMAKE_CXX_STANDARD 17)
+
+add_subdirectory($ENV{ACCL_ROOT}/test/model/bfm ${CMAKE_CURRENT_BINARY_DIR}/bfm)
+add_subdirectory($ENV{ACCL_ROOT}/driver/utils/accl_network_utils
+    ${CMAKE_CURRENT_BINARY_DIR}/accl_network_utils
+)
+
+file(GLOB NODE_SRCS ${CODE_GEN_DIR}/*.cpp $ENV{FINN_ROOT}/deps/cnpy/cnpy.cpp)
+
+add_executable(node_model ${NODE_SRCS})
+
+set(CMAKE_CXX_IMPLICIT_LINK_DIRECTORIES /usr/local/lib ${CMAKE_CXX_IMPLICIT_LINK_DIRECTORIES})
+
+target_link_libraries(node_model PRIVATE z vnx network_roce_v2 zmq zmqpp cclobfm accl_network_utils)
+target_include_directories(node_model PRIVATE
+    $ENV{FINN_ROOT}/src/finn/qnn-data/cpp
+    $ENV{FINN_ROOT}/deps/cnpy
+    $ENV{FINN_ROOT}/deps/finn-hlslib
+    $ENV{FINN_ROOT}/custom_hls
+    $ENV{HLS_PATH}/include
+)
+
+set_target_properties(node_model
+    PROPERTIES
+    RUNTIME_OUTPUT_DIRECTORY ${CODE_GEN_DIR}
+)

custom_hls/accl/funcs.hpp

@@ -0,0 +1,120 @@
+#pragma once
+
+#ifdef CPPSIM
+#include <iostream>
+#endif
+
+const size_t accl_width = 512;
+
+template<unsigned int stream_width, unsigned int num_bits, unsigned int step>
+void accl_out(
+    unsigned int dest_rank,
+    ap_uint<32> comm_adr,
+    ap_uint<32> dpcfg_adr,
+    STREAM<command_word> &cmd_to_cclo,
+    STREAM<command_word> &sts_from_cclo,
+    STREAM<stream_word> &data_to_cclo,
+    hls::stream<ap_uint<stream_width>> &in
+) {
+    STREAM<stream_word> data_from_cclo;
+
+    if (in.empty()) {
+        // Wait until we have some input to make sure that the driver has time to configure
+        // the node.
+        return;
+    }
+
+    ap_uint<32> cflags = 0;
+    ap_uint<32> sflags = 3;
+    accl_hls::ACCLCommand accl(
+        cmd_to_cclo, sts_from_cclo,
+        comm_adr, dpcfg_adr,
+        cflags, sflags
+    );
+    accl_hls::ACCLData data(data_to_cclo, data_from_cclo);
+
+    ap_uint<accl_width> accl_word;
+    ap_uint<stream_width> stream_word;
+
+#ifdef CPPSIM
+    std::cerr << "accl_out starting to output data to rank " << dest_rank << " (" << num_bits << " bits)" << std::endl;
+#endif
+
+    int num_transfer_bits = ((num_bits + accl_width - 1) / accl_width) * accl_width;
+
+    send: for (int i = 0; i < num_bits - step + 1; i += step) {
+        if (i % stream_width == 0) {
+            stream_word = in.read();
+        }
+
+        int ni = i + step - 1;
+
+        accl_word(ni % accl_width, i % accl_width) =
+            stream_word(ni % stream_width, i % stream_width);
+
+        if ((ni + 1) % accl_width == 0) {
+            data.push(accl_word, 0);
+        }
+    }
+
+    if (num_bits < num_transfer_bits) {
+        data.push(accl_word, 0);
+    }
+
+    unsigned int data_from_cclo_id = 9;
+
+    // Currently the hls driver does not allow us to call stream_put in a non-blocking
+    // way. So we call the lower level function directly.
+    accl.start_call(
+        ACCL_SEND, num_transfer_bits / 32,
+        comm_adr, dest_rank, 0, data_from_cclo_id,
+        dpcfg_adr, cflags, sflags | 0x2,
+        0, 0, 0
+    );
+
+#ifdef CPPSIM
+    std::cerr << "accl_out waiting on ack" << std::endl;
+#endif
+
+    accl.finalize_call();
+
+#ifdef CPPSIM
+    std::cerr << "accl_out finished" << std::endl;
+#endif
+}
+
+template<unsigned int stream_width, unsigned int num_bits, unsigned int step>
+void accl_in(
+    unsigned int source,
+    STREAM<stream_word> &data_from_cclo,
+    hls::stream<ap_uint<stream_width>> &out
+) {
+    STREAM<stream_word> data_to_cclo;
+    accl_hls::ACCLData data(data_to_cclo, data_from_cclo);
+
+    ap_uint<accl_width> accl_word;
+    ap_uint<stream_width> stream_word;
+
+#ifdef CPPSIM
+    std::cerr << "accl_in starting to receive data from rank " << source << " (" << num_bits << " bits)" << std::endl;
+#endif
+
+    recv: for (int i = 0; i < num_bits - step + 1; i += step) {
+        if (i % accl_width == 0) {
+            accl_word = data.pull().data;
+        }
+
+        int ni = i + step - 1;
+
+        stream_word(ni % stream_width, i % stream_width) =
+            accl_word(ni % accl_width, i % accl_width);
+
+        if ((ni + 1) % stream_width == 0) {
+            out.write(stream_word);
+        }
+    }
+
+#ifdef CPPSIM
+    std::cerr << "accl_in finished" << std::endl;
+#endif
+}

custom_hls/accl/sim.hpp

@@ -0,0 +1,43 @@
+#include <iostream>
+#include <memory>
+
+#include <accl.hpp>
+#include <accl_network_utils.hpp>
+
+#include "cclo_bfm.h"
+
+std::unique_ptr<ACCL::ACCL> init_accl(
+    unsigned int world_size,
+    unsigned int rank,
+    unsigned int start_port
+) {
+    accl_network_utils::acclDesign design = accl_network_utils::acclDesign::AXIS3x;
+
+    std::vector<ACCL::rank_t> ranks;
+    ranks = accl_network_utils::generate_ranks(true, rank, world_size, start_port, 16 * 1024);
+    return accl_network_utils::initialize_accl(ranks, rank, true, design);
+}
+
+std::unique_ptr<CCLO_BFM> init_cclo_and_wait_for_input(
+    unsigned int zmqport,
+    unsigned int rank,
+    unsigned int world_size,
+    hlslib::Stream<command_word> &cmd_to_cclo,
+    hlslib::Stream<command_word> &sts_from_cclo,
+    hlslib::Stream<stream_word> &data_from_cclo,
+    hlslib::Stream<stream_word> &data_to_cclo
+) {
+    std::vector<unsigned int> dest{9};
+
+    auto cclo = std::make_unique<CCLO_BFM>(zmqport, rank, world_size, dest,
+                    cmd_to_cclo, sts_from_cclo, data_from_cclo, data_to_cclo);
+
+    cclo->run();
+
+    // Makeshift barrier
+    std::cout << "CCLO BFM started" << std::endl;
+    std::string inp;
+    std::cin >> inp;
+
+    return cclo;
+}

docker/Dockerfile.finn

@@ -62,7 +62,19 @@ RUN apt-get update && \
     python-is-python3 \
     python3-pip \
     python3-setuptools-scm \
-    python3-venv
+    python3-venv \
+    # support Coyote
+    cmake \
+    # support ACCL
+    xvfb \
+    libgtk-3-dev \
+    libtinfo5 \
+    doxygen \
+    libboost-dev \
+    libjsoncpp-dev \
+    libtclap-dev \
+    libzmq3-dev
+
 RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config
 RUN locale-gen "en_US.UTF-8"
 
@@ -125,6 +137,11 @@ RUN pip install tokenize-rt==4.2.1
 # pyverilator
 RUN pip install tclwrapper==0.0.1
 
+RUN git clone https://github.com/zeromq/zmqpp && \
+    cd zmqpp && \
+    make && \
+    make install PREFIX=/usr/
+
 # extra environment variables for FINN compiler
 ENV VIVADO_IP_CACHE "/tmp/vivado_ip_cache"
 

src/finn/builder/build_dataflow.py

@@ -34,7 +34,10 @@
 import sys
 import time
 import traceback
+from concurrent import futures
+from copy import deepcopy
 from qonnx.core.modelwrapper import ModelWrapper
+from qonnx.custom_op.registry import getCustomOp
 
 from finn.builder.build_dataflow_config import (
     DataflowBuildConfig,
@@ -108,6 +111,10 @@ def build_dataflow_cfg(model_filename, cfg: DataflowBuildConfig):
     :param model_filename: ONNX model filename to build
     :param cfg: Build configuration
     """
+    # Dispatch a distributed build if we are splitting up the model as part of the build.
+    if cfg.steps is not None and "step_split_dataflow" in cfg.steps:
+        build_distributed_dataflow_cfg(model_filename, cfg)
+
     # if start_step is specified, override the input model
     if cfg.start_step is None:
         print("Building dataflow accelerator from " + model_filename)
@@ -189,6 +196,61 @@ def build_dataflow_cfg(model_filename, cfg: DataflowBuildConfig):
     return 0
 
 
+def run_async_build_iter(cfg, local_cfg, node, i):
+    # TODO: Make the output dir match the rank of the partition
+    local_cfg.output_dir = f"{cfg.output_dir}/{i}"
+
+    node_inst = getCustomOp(node)
+    child_model_filename = node_inst.get_nodeattr("model")
+
+    print(f"Launching build for partition {i}")
+    build_dataflow_cfg(child_model_filename, local_cfg)
+
+
+def build_distributed_dataflow_cfg(model_filename, cfg: DataflowBuildConfig):
+    steps = resolve_build_steps(cfg, partial=False)
+    step_names = list(map(lambda x: x.__name__, steps))
+
+    # TODO: Not sure if splitting up the config implicitly up is the best way to do this.
+    # Maybe it would be better for the user to explicitly provide global and local build
+    # configs.
+
+    split_step = "step_split_dataflow"
+    if split_step not in step_names:
+        print("Dataflow should be split up as part of distributed build")
+        return -1
+
+    split_idx = step_names.index(split_step) + 1
+
+    global_cfg = deepcopy(cfg)
+    global_cfg.steps = steps[:split_idx]
+
+    local_cfg = deepcopy(cfg)
+    local_cfg.steps = steps[split_idx:]
+
+    if not cfg.save_intermediate_models:
+        print("save_intermediate_models must be enabled for distributed build")
+        return -1
+
+    if not cfg.start_step or cfg.start_step in step_names[:split_idx]:
+        if build_dataflow_cfg(model_filename, global_cfg) != 0:
+            print("Global build failed")
+            return -1
+
+        local_cfg.start_step = None
+
+    if cfg.stop_step and cfg.stop_step in step_names[:split_idx]:
+        return 0
+
+    intermediate_models_dir = cfg.output_dir + "/intermediate_models"
+    parent_model = ModelWrapper(f"{intermediate_models_dir}/{split_step}.onnx")
+
+    sdp_nodes = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")
+    with futures.ProcessPoolExecutor() as pool:
+        for i, node in enumerate(sdp_nodes):
+            pool.submit(run_async_build_iter, cfg, local_cfg, node, i)
+
+
 def build_dataflow_directory(path_to_cfg_dir: str):
     """Best-effort build a dataflow accelerator from the specified directory.
 

src/finn/builder/build_dataflow_config.py

@@ -50,6 +50,7 @@ class ShellFlowType(str, Enum):
 
     VIVADO_ZYNQ = "vivado_zynq"
     VITIS_ALVEO = "vitis_alveo"
+    COYOTE_ALVEO = "coyote_alveo"
 
 
 class DataflowOutputType(str, Enum):
@@ -104,6 +105,8 @@ class VerificationStepType(str, Enum):
     STREAMLINED_PYTHON = "streamlined_python"
     #: verify after step_apply_folding_config, using C++ for each HLS node
     FOLDED_HLS_CPPSIM = "folded_hls_cppsim"
+    #: verify after step_insert_accl, using C++ for each HLS node
+    ACCL_HLS_CPPSIM = "insert_accl"
     #: verify after step_create_stitched_ip, using stitched-ip Verilog
     STITCHED_IP_RTLSIM = "stitched_ip_rtlsim"
 
@@ -291,18 +294,21 @@ class DataflowBuildConfig:
 
     #: Which Vitis platform will be used.
     #: Only relevant when `shell_flow_type = ShellFlowType.VITIS_ALVEO`
+    # or `shell_flow_type = ShellFlowType.COYOTE_ALVEO`
     #: e.g. "xilinx_u250_xdma_201830_2"
     #: If not specified but "board" is specified, will use the FINN
     #: default (if any) for that Alveo board
     vitis_platform: Optional[str] = None
 
     #: Path to JSON config file assigning each layer to an SLR.
     #: Only relevant when `shell_flow_type = ShellFlowType.VITIS_ALVEO`
+    # or `shell_flow_type = ShellFlowType.COYOTE_ALVEO`
     #: Will be applied with :py:mod:`qonnx.transformation.general.ApplyConfig`
     vitis_floorplan_file: Optional[str] = None
 
     #: Vitis optimization strategy
     #: Only relevant when `shell_flow_type = ShellFlowType.VITIS_ALVEO`
+    # or `shell_flow_type = ShellFlowType.COYOTE_ALVEO`
     vitis_opt_strategy: Optional[VitisOptStrategyCfg] = VitisOptStrategyCfg.DEFAULT
 
     #: Whether intermediate ONNX files will be saved during the build process.
@@ -361,7 +367,10 @@ def _resolve_hls_clk_period(self):
     def _resolve_driver_platform(self):
         if self.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
             return "zynq-iodma"
-        elif self.shell_flow_type == ShellFlowType.VITIS_ALVEO:
+        elif (
+            self.shell_flow_type == ShellFlowType.VITIS_ALVEO
+            or self.shell_flow_type == ShellFlowType.COYOTE_ALVEO
+        ):
             return "alveo"
         else:
             raise Exception("Couldn't resolve driver platform for " + str(self.shell_flow_type))
@@ -371,7 +380,10 @@ def _resolve_fpga_part(self):
             # lookup from part map if not specified
             if self.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
                 return pynq_part_map[self.board]
-            elif self.shell_flow_type == ShellFlowType.VITIS_ALVEO:
+            elif (
+                self.shell_flow_type == ShellFlowType.VITIS_ALVEO
+                or self.shell_flow_type == ShellFlowType.COYOTE_ALVEO
+            ):
                 return alveo_part_map[self.board]
             else:
                 raise Exception("Couldn't resolve fpga_part for " + self.board)
@@ -406,7 +418,7 @@ def _resolve_vitis_platform(self):
             return alveo_default_platform[self.board]
         else:
             raise Exception(
-                "Could not resolve Vitis platform:" " need either board or vitis_platform specified"
+                "Could not resolve Vitis platform: need either board or vitis_platform specified"
             )
 
     def _resolve_verification_steps(self):