Replace aie2_set_bf512_bf256, aie2_ext_bf256_bf512 with aie2_set_I512…

…_I256, aie2_ext_I256_I512
Xilinx · Nov 27, 2024 · 8c616e1 · 8c616e1
1 parent c52bfcb
commit 8c616e1
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Showing 10 changed files with 113 additions and 128 deletions.
diff --git a/clang/include/clang/Basic/BuiltinsAIE.def b/clang/include/clang/Basic/BuiltinsAIE.def
@@ -311,7 +311,6 @@ BUILTIN(__builtin_aiev2_set_I64_I32,"V2iii","nc")
 BUILTIN(__builtin_aiev2_set_I512_I256,"V16iV8ii","nc")
 BUILTIN(__builtin_aiev2_set_I1024_I512,"V32iV16ii","nc")
 BUILTIN(__builtin_aiev2_set_I1024_I256,"V32iV8ii","nc")
-BUILTIN(__builtin_aiev2_set_bf512_bf256, "V32yV16yi","nc")
 BUILTIN(__builtin_aiev2_set_bf1024_bf512,"V64yV32yi","nc")
 BUILTIN(__builtin_aiev2_set_bf1024_bf256,"V64yV16yi","nc")
 BUILTIN(__builtin_aiev2_set_ACC512_ACC256,"V16nV8ni","nc")
@@ -322,7 +321,6 @@ BUILTIN(__builtin_aiev2_ext_I32_I64,"iV2ii","nc")
 BUILTIN(__builtin_aiev2_ext_I256_I512,"V8iV16ii","nc")
 BUILTIN(__builtin_aiev2_ext_I512_I1024,"V16iV32ii","nc")
 BUILTIN(__builtin_aiev2_ext_I256_I1024,"V8iV32ii","nc")
-BUILTIN(__builtin_aiev2_ext_bf256_bf512, "V16yV32yi","nc")
 BUILTIN(__builtin_aiev2_ext_bf512_bf1024,"V32yV64yi","nc")
 BUILTIN(__builtin_aiev2_ext_bf256_bf1024,"V16yV64yi","nc")
 BUILTIN(__builtin_aiev2_ext_ACC256_ACC512,"V8nV16ni","nc")

diff --git a/clang/lib/Headers/aiev2_upd_ext.h b/clang/lib/Headers/aiev2_upd_ext.h
@@ -511,9 +511,9 @@ INTRINSIC(v8cint32) concat(v4cint32 a0, v4cint32 a1) {
 // Extract 256-bit portion from 512-bit register
 INTRINSIC(v16bfloat16) extract_v16bfloat16(v32bfloat16 a, int idx) {
   if (idx == 0)
-    return __builtin_aiev2_ext_bf256_bf512(a, 0);
+    return __builtin_aiev2_ext_I256_I512(a, 0);
   else
-    return __builtin_aiev2_ext_bf256_bf512(a, 1);
+    return __builtin_aiev2_ext_I256_I512(a, 1);
 }
 
 // Insert 256-bit in 512-bit register
@@ -527,9 +527,9 @@ INTRINSIC(v32bfloat16) insert(v32bfloat16 a, int idx, v16bfloat16 b) {
 // Set 256-bit portion of 512-bit register
 INTRINSIC(v32bfloat16) set_v32bfloat16(int idx, v16bfloat16 b) {
   if (idx == 0)
-    return __builtin_aiev2_set_bf512_bf256(b, 0);
+    return __builtin_aiev2_set_I512_I256(b, 0);
   else
-    return __builtin_aiev2_set_bf512_bf256(b, 1);
+    return __builtin_aiev2_set_I512_I256(b, 1);
 }
 
 INTRINSIC(v32bfloat16) concat(v16bfloat16 a0, v16bfloat16 a1) {

diff --git a/clang/test/CodeGen/aie/aie2/aie2-upd-ext-intrinsic.cpp b/clang/test/CodeGen/aie/aie2/aie2-upd-ext-intrinsic.cpp
@@ -1651,8 +1651,10 @@ v16float test_extract_v16float(v32float a, int idx) {
 
 // CHECK-LABEL: @_Z24test_extract_v16bfloat16Dv32_u6__bf16i(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call noundef <16 x bfloat> @llvm.aie2.ext.bf256.bf512(<32 x bfloat> [[A:%.*]], i32 0)
-// CHECK-NEXT:    ret <16 x bfloat> [[TMP0]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <32 x bfloat> [[A:%.*]] to <16 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i32> @llvm.aie2.ext.I256.I512(<16 x i32> [[TMP0]], i32 0)
+// CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to <16 x bfloat>
+// CHECK-NEXT:    ret <16 x bfloat> [[TMP2]]
 //
 v16bfloat16 test_extract_v16bfloat16(v32bfloat16 a, int idx) {
     return extract_v16bfloat16(a, 0);
@@ -1669,8 +1671,10 @@ v32bfloat16 test_insert(v32bfloat16 a, int idx, v16bfloat16 b) {
 
 // CHECK-LABEL: @_Z20test_set_v32bfloat16iDv16_u6__bf16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call <32 x bfloat> @llvm.aie2.set.bf512.bf256(<16 x bfloat> [[B:%.*]], i32 1)
-// CHECK-NEXT:    ret <32 x bfloat> [[TMP0]]
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x bfloat> [[B:%.*]] to <8 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i32> @llvm.aie2.set.I512.I256(<8 x i32> [[TMP0]], i32 1)
+// CHECK-NEXT:    [[RETVAL_0_I:%.*]] = bitcast <16 x i32> [[TMP1]] to <32 x bfloat>
+// CHECK-NEXT:    ret <32 x bfloat> [[RETVAL_0_I]]
 //
 v32bfloat16 test_set_v32bfloat16(int idx, v16bfloat16 b) {
     return set_v32bfloat16(1, b);
@@ -1822,8 +1826,8 @@ v8bfloat16 test_extract_v8bfloat16_512(v32bfloat16 a, int idx) {
 
 // CHECK-LABEL: @_Z27test_extract_v8bfloat16_256Dv16_u6__bf16i(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call <32 x bfloat> @llvm.aie2.set.bf512.bf256(<16 x bfloat> [[A:%.*]], i32 0)
-// CHECK-NEXT:    [[TMP1:%.*]] = bitcast <32 x bfloat> [[TMP0]] to <16 x i32>
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x bfloat> [[A:%.*]] to <8 x i32>
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i32> @llvm.aie2.set.I512.I256(<8 x i32> [[TMP0]], i32 0)
 // CHECK-NEXT:    [[TMP2:%.*]] = tail call noundef <32 x bfloat> @llvm.aie2.v32bfloat16()
 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <32 x bfloat> [[TMP2]] to <16 x i32>
 // CHECK-NEXT:    [[MUL_I_I:%.*]] = shl nsw i32 [[IDX:%.*]], 4

diff --git a/llvm/include/llvm/IR/IntrinsicsAIE2.td b/llvm/include/llvm/IR/IntrinsicsAIE2.td
@@ -263,8 +263,6 @@ class AIEV2SET_I1024_I512
      : Intrinsic<[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], [IntrNoMem]>;
 class AIEV2SET_I1024_I256
      : Intrinsic<[llvm_v32i32_ty], [llvm_v8i32_ty,llvm_i32_ty], [IntrNoMem]>;
-class AIEV2SET_bf512_bf256
-     : Intrinsic<[llvm_v32bf16_ty], [llvm_v16bf16_ty,llvm_i32_ty], [IntrNoMem]>;
 class AIEV2SET_bf1024_bf512
      : Intrinsic<[llvm_v64bf16_ty], [llvm_v32bf16_ty,llvm_i32_ty], [IntrNoMem]>;
 class AIEV2SET_bf1024_bf256
@@ -284,8 +282,6 @@ class AIEV2EXT_I512_I1024
      : Intrinsic<[llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], [IntrNoMem]>;
 class AIEV2EXT_I256_I1024
      : Intrinsic<[llvm_v8i32_ty] , [llvm_v32i32_ty,llvm_i32_ty], [IntrNoMem]>;
-class AIEV2EXT_bf256_bf512
-     : Intrinsic<[llvm_v16bf16_ty] , [llvm_v32bf16_ty,llvm_i32_ty], [IntrNoMem]>;
 class AIEV2EXT_bf512_bf1024
      : Intrinsic<[llvm_v32bf16_ty], [llvm_v64bf16_ty,llvm_i32_ty], [IntrNoMem]>;
 class AIEV2EXT_bf256_bf1024
@@ -759,7 +755,6 @@ def int_aie2_set_I64_I32    : ClangBuiltin<"__builtin_aiev2_set_I64_I32">,    AI
 def int_aie2_set_I512_I256  : ClangBuiltin<"__builtin_aiev2_set_I512_I256">,  AIEV2SET_I512_I256;
 def int_aie2_set_I1024_I512 : ClangBuiltin<"__builtin_aiev2_set_I1024_I512">, AIEV2SET_I1024_I512;
 def int_aie2_set_I1024_I256 : ClangBuiltin<"__builtin_aiev2_set_I1024_I256">, AIEV2SET_I1024_I256;
-def int_aie2_set_bf512_bf256  : ClangBuiltin<"__builtin_aiev2_set_bf512_bf256">,  AIEV2SET_bf512_bf256;
 def int_aie2_set_bf1024_bf512 : ClangBuiltin<"__builtin_aiev2_set_bf1024_bf512">, AIEV2SET_bf1024_bf512;
 def int_aie2_set_bf1024_bf256 : ClangBuiltin<"__builtin_aiev2_set_bf1024_bf256">, AIEV2SET_bf1024_bf256;
 def int_aie2_set_512_256_acc  :
@@ -773,7 +768,6 @@ def int_aie2_ext_I32_I64    : ClangBuiltin<"__builtin_aiev2_ext_I32_I64">,    AI
 def int_aie2_ext_I256_I512  : ClangBuiltin<"__builtin_aiev2_ext_I256_I512">,  AIEV2EXT_I256_I512;
 def int_aie2_ext_I512_I1024 : ClangBuiltin<"__builtin_aiev2_ext_I512_I1024">, AIEV2EXT_I512_I1024;
 def int_aie2_ext_I256_I1024 : ClangBuiltin<"__builtin_aiev2_ext_I256_I1024">, AIEV2EXT_I256_I1024;
-def int_aie2_ext_bf256_bf512  : ClangBuiltin<"__builtin_aiev2_ext_bf256_bf512">,  AIEV2EXT_bf256_bf512;
 def int_aie2_ext_bf512_bf1024 : ClangBuiltin<"__builtin_aiev2_ext_bf512_bf1024">, AIEV2EXT_bf512_bf1024;
 def int_aie2_ext_bf256_bf1024 : ClangBuiltin<"__builtin_aiev2_ext_bf256_bf1024">, AIEV2EXT_bf256_bf1024;
 

diff --git a/llvm/lib/Target/AIE/AIE2InstrInfo.cpp b/llvm/lib/Target/AIE/AIE2InstrInfo.cpp
@@ -1404,7 +1404,6 @@ AIE2InstrInfo::getVExtractOpInfo(const MachineInstr &MI) const {
   case Intrinsic::aie2_ext_I512_I1024:
   case Intrinsic::aie2_ext_I256_I1024:
 
-  case Intrinsic::aie2_ext_bf256_bf512:
   case Intrinsic::aie2_ext_bf512_bf1024:
   case Intrinsic::aie2_ext_bf256_bf1024:
 

diff --git a/llvm/lib/Target/AIE/AIE2InstrPatterns.td b/llvm/lib/Target/AIE/AIE2InstrPatterns.td
@@ -891,12 +891,10 @@ def : Pat<(int_aie2_upd_1024_256_acc ACC1024:$src1, ACC256:$src2, 0x3),
             sub_512_hi)>;
 
 // Set
-foreach intr = [int_aie2_set_I512_I256, int_aie2_set_bf512_bf256] in {
-  def : Pat<(intr VEC256:$src, 0x0),
-             (REG_SEQUENCE VEC512, VEC256:$src, sub_256_lo)>;
-  def : Pat<(intr VEC256:$src, 0x1),
-             (REG_SEQUENCE VEC512, VEC256:$src, sub_256_hi)>;
-}
+def : Pat<(int_aie2_set_I512_I256 VEC256:$src, 0x0),
+            (REG_SEQUENCE VEC512, VEC256:$src, sub_256_lo)>;
+def : Pat<(int_aie2_set_I512_I256 VEC256:$src, 0x1),
+            (REG_SEQUENCE VEC512, VEC256:$src, sub_256_hi)>;
 foreach intr = [int_aie2_set_I1024_I512, int_aie2_set_bf1024_bf512] in {
   def : Pat<(intr VEC512:$src, 0x0),
              (REG_SEQUENCE VEC1024, VEC512:$src, sub_512_lo)>;
@@ -999,10 +997,6 @@ def : Pat<(int_aie2_ext_I256_I1024 VEC1024:$src, 0x2),
            (v8i32 (EXTRACT_SUBREG VEC1024:$src, sub_512_hi_256_lo))>;
 def : Pat<(int_aie2_ext_I256_I1024 VEC1024:$src, 0x3),
            (v8i32 (EXTRACT_SUBREG VEC1024:$src, sub_512_hi_256_hi))>;
-def : Pat<(int_aie2_ext_bf256_bf512 VEC512:$src, 0x0),
-           (v16bf16 (EXTRACT_SUBREG VEC512:$src, sub_256_lo))>;
-def : Pat<(int_aie2_ext_bf256_bf512 VEC512:$src, 0x1),
-           (v16bf16 (EXTRACT_SUBREG VEC512:$src, sub_256_hi))>;
 def : Pat<(int_aie2_ext_bf512_bf1024 VEC1024:$src, 0x0),
            (v32bf16 (EXTRACT_SUBREG VEC1024:$src, sub_512_lo))>;
 def : Pat<(int_aie2_ext_bf512_bf1024 VEC1024:$src, 0x1),

diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-extract.mir b/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-extract.mir
@@ -399,28 +399,6 @@ body:             |
     PseudoRET implicit $lr, implicit $x0
 ...
 
----
-name:            ext_256_512_bf
-alignment:       16
-legalized:       true
-regBankSelected: true
-body:             |
-  bb.1.entry:
-    liveins: $r0, $x2
-    ; CHECK-LABEL: name: ext_256_512_bf
-    ; CHECK: liveins: $r0, $x2
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ewl = COPY [[COPY]].sub_256_lo
-    ; CHECK-NEXT: $wl0 = COPY [[COPY1]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wl0
-    %1:vregbank(<32 x s16>) = COPY $x2
-    %3:gprregbank(s32) = G_CONSTANT i32 0
-    %0:vregbank(<16 x s16>) = G_INTRINSIC intrinsic(@llvm.aie2.ext.bf256.bf512), %1:vregbank(<32 x s16>), %3:gprregbank(s32)
-    $wl0 = COPY %0:vregbank(<16 x s16>)
-    PseudoRET implicit $lr, implicit $wl0
-...
-
 ---
 name:            ext_256_1024_bf
 alignment:       16

diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-set.mir b/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-set.mir
@@ -258,25 +258,3 @@ body:             |
     $wl0 = COPY %0:vregbank(<16 x s16>)
     PseudoRET implicit $lr, implicit $wl0
 ...
-
----
-name:            set_512_256_bf
-alignment:       16
-legalized:       true
-regBankSelected: true
-body:             |
-  bb.1.entry:
-    liveins: $r0, $wl2
-    ; CHECK-LABEL: name: set_512_256_bf
-    ; CHECK: liveins: $r0, $wl2
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:ewh = COPY $wl2
-    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec512 = REG_SEQUENCE [[COPY]], %subreg.sub_256_hi
-    ; CHECK-NEXT: $x0 = COPY [[REG_SEQUENCE]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
-    %2:vregbank(<16 x s16>) = COPY $wl2
-    %3:gprregbank(s32) = G_CONSTANT i32 1
-    %0:vregbank(<32 x s16>) = G_INTRINSIC intrinsic(@llvm.aie2.set.bf512.bf256), %2:vregbank(<16 x s16>), %3:gprregbank(s32)
-    $x0 = COPY %0:vregbank(<32 x s16>)
-    PseudoRET implicit $lr, implicit $x0
-...