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[AIEX] Properly constrain addressing register classes in PostSelectOp…
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…timize to satisfy MachineVerifier
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@khallouh
khallouh committed Feb 13, 2025
1 parent cc26b98 commit c9293ea
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Showing 8 changed files with 90 additions and 55 deletions.
8 changes: 8 additions & 0 deletions llvm/lib/Target/AIE/AIE2RegisterInfo.cpp
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Expand Up @@ -364,6 +364,14 @@ AIE2RegisterInfo::getMinClassForRegBank(const RegisterBank &RB, LLT Ty) const {
llvm_unreachable("Unexpected register bank.");
}

bool AIE2RegisterInfo::constrainAddrRegClass(MachineRegisterInfo &MRI,
Register Reg) const {
return (MRI.constrainRegClass(Reg, &AIE2::eDC_as_32BitRegClass) ||
MRI.constrainRegClass(Reg, &AIE2::eDN_as_32BitRegClass) ||
MRI.constrainRegClass(Reg, &AIE2::eDJ_as_32BitRegClass) ||
MRI.constrainRegClass(Reg, &AIE2::eM_as_32BitRegClass));
}

const TargetRegisterClass *AIE2RegisterInfo::getConstrainedRegClassForOperand(
const MachineOperand &MO, const MachineRegisterInfo &MRI) const {
// AIE has classes with mixed types, which aren't properly handled in llvm.
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3 changes: 3 additions & 0 deletions llvm/lib/Target/AIE/AIE2RegisterInfo.h
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Expand Up @@ -99,6 +99,9 @@ struct AIE2RegisterInfo : public AIE2GenRegisterInfo {
const TargetRegisterClass *getAddrCountRegClass() const override {
return &AIE2::eDCRegClass;
}

bool constrainAddrRegClass(MachineRegisterInfo &MRI,
Register Reg) const override;
};
} // namespace llvm

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5 changes: 5 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseRegisterInfo.h
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Expand Up @@ -99,6 +99,11 @@ struct AIEBaseRegisterInfo : public TargetRegisterInfo {
virtual const TargetRegisterClass *getAddrCountRegClass() const {
llvm_unreachable("Target didn't implement getAddrCountRegClass!");
}

virtual bool constrainAddrRegClass(MachineRegisterInfo &MRI,
Register Reg) const {
llvm_unreachable("Target didn't implement constrainAddrRegClass!");
}
};

} // namespace llvm
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11 changes: 9 additions & 2 deletions llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -364,7 +364,7 @@ static void collectIteratorComponentsUsage(
static bool tryToDuplicateLoadUse(
DenseMap<Register, SmallPtrSet<MachineInstr *, 8>> &LoadUses,
SmallSet<Register, 8> &NonLoadUses, MachineRegisterInfo &MRI,
const AIEBaseInstrInfo *TII) {
const AIEBaseInstrInfo *TII, const AIEBaseRegisterInfo *TRI) {

bool Changed = false;
for (auto &RegMILoad : LoadUses) {
Expand All @@ -377,6 +377,13 @@ static bool tryToDuplicateLoadUse(
MachineInstr *DefReg = MRI.getUniqueVRegDef(Reg);

MachineBasicBlock::iterator InsertPoint = DefReg->getIterator();

// AIE's PseudoMove instruction takes compound register classes which
// contains registers of different sizes. We need to use the right classes
// to avoid the MachineVerifier complaining about mismatching sizes.
assert(TRI->constrainAddrRegClass(MRI, Reg) &&
"Expected an addressing register class");

Register DstReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
// Here we cannot use COPY, because Machine CSE will run
// PerformTrivialCopyPropagation and our work will disappear.
Expand Down Expand Up @@ -437,7 +444,7 @@ bool duplicateAdressingRegs(MachineBasicBlock &MBB, MachineRegisterInfo &MRI) {
// The second part, filter the real useful cases,
// registers used in both load and stores (or non load uses).
// Then duplicate those registers.
return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII);
return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII, TRI);
}

using Operation = AIEBaseInstrInfo::AbstractOp::OperationType;
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8 changes: 8 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -376,6 +376,14 @@ AIE2PRegisterInfo::getMinClassForRegBank(const RegisterBank &RB, LLT Ty) const {
llvm_unreachable("Unexpected register bank.");
}

bool AIE2PRegisterInfo::constrainAddrRegClass(MachineRegisterInfo &MRI,
Register Reg) const {
return (MRI.constrainRegClass(Reg, &AIE2P::eDC_as_32BitRegClass) ||
MRI.constrainRegClass(Reg, &AIE2P::eDN_as_32BitRegClass) ||
MRI.constrainRegClass(Reg, &AIE2P::eDJ_as_32BitRegClass) ||
MRI.constrainRegClass(Reg, &AIE2P::eM_as_32BitRegClass));
}

const TargetRegisterClass *AIE2PRegisterInfo::getConstrainedRegClassForOperand(
const MachineOperand &MO, const MachineRegisterInfo &MRI) const {
// AIE has classes with mixed types, which aren't properly handled in llvm.
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -98,6 +98,10 @@ struct AIE2PRegisterInfo : public AIE2PGenRegisterInfo {
const TargetRegisterClass *getAddrCountRegClass() const override {
return &AIE2P::eDCRegClass;
}

bool constrainAddrRegClass(MachineRegisterInfo &MRI,
Register Reg) const override;

bool isVecOrAccRegClass(const TargetRegisterClass &RC) const override;

bool isFifoPhysReg(const Register Reg) const override;
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54 changes: 27 additions & 27 deletions llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -4,18 +4,18 @@
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates

# RUN: llc -mtriple aie2 -run-pass=aie-post-select-optimize %s -o - | FileCheck %s
# RUN: llc -mtriple aie2 -start-before=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2 -run-pass=aie-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple aie2 -start-before=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=POST-COALESCER
# RUN: llc -mtriple aie2 -start-after=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2 -start-after=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=COALESCER

# POST-COALESCER represents the case where we apply the post-select optimization and we
# stop after the coalescer. This case shows the optimized version.
# COALESCER represents the case where we don't apply the post-select optimization and we
# stop after the coalescer.
# stop after the coalescer.

---
name: two2d_descriptors
Expand All @@ -33,15 +33,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -77,7 +77,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm10_pseudo]].sub_dim_stride
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand All @@ -104,7 +104,7 @@ body: |
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm10_pseudo 14
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -167,21 +167,21 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo5:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo6:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -225,7 +225,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_size
; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_stride
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -260,7 +260,7 @@ body: |
; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm10_pseudo 0
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm10_pseudo 16
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down
52 changes: 26 additions & 26 deletions llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates

# RUN: llc -mtriple aie2p -run-pass=aie-post-select-optimize %s -o - | FileCheck %s
# RUN: llc -mtriple aie2p -start-before=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2p -run-pass=aie-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple aie2p -start-before=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=POST-COALESCER
# RUN: llc -mtriple aie2p -start-after=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2p -start-after=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=COALESCER

# POST-COALESCER represents the case where we apply the post-select optimization and we
Expand All @@ -33,15 +33,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -77,7 +77,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm11_pseudo]].sub_dim_stride
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand All @@ -104,7 +104,7 @@ body: |
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm11_pseudo 14
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -167,21 +167,21 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo5:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo6:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -225,7 +225,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_size
; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_stride
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -260,7 +260,7 @@ body: |
; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm11_pseudo 0
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm11_pseudo 16
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down

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