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[AIE2P] Implemented VST.PACK combine #280
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CombOpIntrinsicID != Intrinsic::aie2p_pack_I1024_I4_I8) | ||
return {}; | ||
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assert((getLoadStoreSize(MemOp) == 256) && "Unexpected STS.SRS size"); |
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nit: VST.PACK
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auto Opcode = TII.getMvSclMultiSlotPseudoOpcode(); | ||
MIB.setInstr(*NewInstr); | ||
MIB.buildInstr(Opcode, {AIE2P::crPackSize}, {}).addImm((unsigned)Is8Bit); |
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Oh, this crPackSize usage is very subtle in the documentation.
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true
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This is not the only place were we have to set a control register. Can we create a function for this in AIEBaseInstructionSelector.cpp
, as we did with setUnsetCtrlRegister
?
// Selects the size of the Pack instructions | ||
// 0 – Destination is 4 bits | ||
// 1 – Destination is 8 bits | ||
bool Is8Bit = cast<GIntrinsic>(PackOp)->getIntrinsicID() == |
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nit: const.
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llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-postinc-2d-vst_pack.mir
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; CHECK-NEXT: $packsign0 = MOV_scalar_imm11_pseudo 0 | ||
; CHECK-NEXT: [[COPY3:%[0-9]+]]:edj = COPY $dj0 | ||
; CHECK-NEXT: $crpacksize = MOV_scalar_imm11_pseudo 1 | ||
; CHECK-NEXT: $packsign0 = COPY [[COPY2]] |
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Curious: We have two packSign
registers in AIE2p? I assume both are addressible, and here this is just an arbitrary choice to use packsign0
for the dynamic case?
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yes, we have two packSign
registers in AIE2p, packSign0
and packSign1
. We have the same situation for vaddSign
, unpackSign
, upsSign
, srsSign
. In all cases for the dynamic case we just use the instruction with the xxxSign0
.
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LGTM, I couldn't spot something wrong. I have checked about half of the tests, and trust the rest are correct as well. Up to you if you want to seek another review from AIE2p core team :)
Before merging, maybe have a QoR run to check those combines are used in practice and do not introduce new failures.
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Please go through all test files and fix the types and sizes of all vectors involved.
aie2p_pack_I512_I8_I16
: the input vector should be<32 x s16>
and the output one<32 x s8>
aie2p_pack_I512_I4_I8
: the input vector should be<64 x s8>
and the output one<64 x s4>
aie2p_pack_I1024_I8_I16
: the input vector should be<64 x s16>
and the output one<64 x s8>
aie2p_pack_I1024_I4_I8
: the input vector should be<128 x s8>
and the output one<128 x s4>
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Could you update the header of this file to 2024-2025
?
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Please update this header as well: 2023-2025
if (CombOp.getOpcode() != AIE2P::G_INTRINSIC_W_SIDE_EFFECTS) | ||
return false; |
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This check is duplicated, we also check this in getCombinedOpcodePACK
. I would prefer to just keep it in getCombinedOpcodePACK
.
assert((MemOpLoadStoreSize == 256 && | ||
(SrcRegSize == 512 || SrcRegSize == 1024)) && | ||
"Unexpected VST.PACK size"); |
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In AIE2P the store size can be 512 bits if the source register size is 1024. I would suggest updating the assert to:
assert((MemOpLoadStoreSize == 256 && SrcRegSize == 512) || (MemOpLoadStoreSize == 512 && SrcRegSize == 1024))
CombOpIntrinsicID != Intrinsic::aie2p_pack_I1024_I4_I8) | ||
return {}; | ||
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assert((getLoadStoreSize(MemOp) == 256) && "Unexpected VST.PACK size"); |
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As mentioned in another comment the memory size can either be 256 or 512 in AIE2P.
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auto Opcode = TII.getMvSclMultiSlotPseudoOpcode(); | ||
MIB.setInstr(*NewInstr); | ||
MIB.buildInstr(Opcode, {AIE2P::crPackSize}, {}).addImm((unsigned)Is8Bit); |
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This is not the only place were we have to set a control register. Can we create a function for this in AIEBaseInstructionSelector.cpp
, as we did with setUnsetCtrlRegister
?
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