Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[AIE2P] Implemented VLDB.UNPACK combine #299

Merged
merged 2 commits into from
Feb 5, 2025
Merged

[AIE2P] Implemented VLDB.UNPACK combine #299

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
9c1a780
[AIEX] Add setCtrlRegister method to InstructionSelector.
katerynamuts Feb 5, 2025
de96091
[AIE2P] Implemented VLDB.UNPACK combine
katerynamuts Feb 5, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
21 changes: 13 additions & 8 deletions llvm/lib/Target/AIE/AIE2InstructionSelector.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,6 @@ class AIE2InstructionSelector : public AIEBaseInstructionSelector {
Register createSparseRegSequence(Register Vec, Register Mask,
MachineRegisterInfo &MRI);
void insertPtrAddForOffset(MachineRegisterInfo &MRI, MachineInstr &MemI);
void setCtrlRegister(MachineInstr &I, MachineRegisterInfo &MRI,
Register CRReg, Register ValueReg);

bool select(MachineInstr &I) override;
bool selectCascadeStreamInsn(MachineInstr &I, MachineRegisterInfo &MRI,
Expand Down Expand Up @@ -150,6 +148,11 @@ class AIE2InstructionSelector : public AIEBaseInstructionSelector {
std::optional<APInt> Immediate, bool IsSigned,
bool Is32Lanes);
bool canCombinePACK(MachineInstr &MemOp, MachineInstr &CombOp);
bool canCombineUNPACKLoad(MachineInstr &MemOp, MachineInstr &CombOp,
MachineRegisterInfo &MRI);
std::optional<LoadStoreOpcodes> getCombinedOpcodeUNPACKLoad(
const MachineInstr &MemOp, const MachineInstr &CombOp,
std::optional<APInt> Immediate, MachineRegisterInfo &MRI);

// const AIE2TargetMachine &TM;
const AIE2InstrInfo &TII;
Expand Down Expand Up @@ -821,7 +824,8 @@ bool AIE2InstructionSelector::selectVPACK(MachineInstr &I,
return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
}

std::optional<LoadStoreOpcodes> getCombinedOpcodeUNPACKLoad(
std::optional<LoadStoreOpcodes>
AIE2InstructionSelector::getCombinedOpcodeUNPACKLoad(
const MachineInstr &MemOp, const MachineInstr &CombOp,
std::optional<APInt> Immediate, MachineRegisterInfo &MRI) {

Expand Down Expand Up @@ -912,8 +916,9 @@ std::optional<LoadStoreOpcodes> getCombinedOpcodeUNPACKLoad(
return {};
}

bool canCombineUNPACKLoad(MachineInstr &MemOp, MachineInstr &CombOp,
MachineRegisterInfo &MRI) {
bool AIE2InstructionSelector::canCombineUNPACKLoad(MachineInstr &MemOp,
MachineInstr &CombOp,
MachineRegisterInfo &MRI) {
const std::optional<APInt> NoImmediate = {};
return getCombinedOpcodeUNPACKLoad(MemOp, CombOp, NoImmediate, MRI)
.has_value();
Expand Down Expand Up @@ -952,6 +957,8 @@ bool AIE2InstructionSelector::selectG_AIE_LOAD_UNPACK(
std::optional<LoadStoreOpcodes> LSO = getCombinedOpcodeUNPACKLoad(
AMI->MemI, UNPACKI, AMI->ImmediateOffset, MRI);

assert(LSO && "Unexpected VLDB.UNPACK combine failure");

Register DstReg = UNPACKI.getOperand(0).getReg();
Register SignReg = UNPACKI.getOperand(3).getReg();

Expand Down Expand Up @@ -2380,9 +2387,7 @@ bool AIE2InstructionSelector::selectSetControlRegister(
break;
}

MachineInstrBuilder MI =
MIB.buildInstr(AIE2::MOV_scalar_imm10_pseudo, {CtrlReg}, {})
.addImm(SrcConstVal);
MachineInstrBuilder MI = setCtrlRegister(MIB, CtrlReg, SrcConstVal);
I.eraseFromParent();
return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
}
Expand Down
26 changes: 16 additions & 10 deletions llvm/lib/Target/AIE/AIEBaseInstructionSelector.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
/// \file
Expand Down Expand Up @@ -242,6 +242,13 @@ void AIEBaseInstructionSelector::setUnsetCtrlRegister(
setUnsetCtrlRegister(MIB, I, I, MRI, CRReg, ValueReg, DefaultCRVal);
}

MachineInstrBuilder
AIEBaseInstructionSelector::setCtrlRegister(MachineIRBuilder &MIB,
Register CRReg, unsigned Val) {
auto Opcode = TII.getMvSclMultiSlotPseudoOpcode();
return MIB.buildInstr(Opcode, {CRReg}, {}).addImm(Val);
}

void AIEBaseInstructionSelector::addSplitMemOperands(
MachineInstr &I, MachineInstrBuilder &Higher, MachineInstrBuilder &Lower,
unsigned Offset, unsigned SplitFactor) {
Expand Down Expand Up @@ -707,14 +714,6 @@ bool AIEBaseInstructionSelector::selectG_AIE_LOAD_CONV(
NewInstr.cloneMemRefs(AMI->MemI);

CONVI.eraseFromParent();

// Erasing the load instruction breaks later on in the selection code. That is
// because an iterator is kept on erased instructions. This breaks while
// trying to eliminate a trivially dead instruction which requires access to
// its memory operands which have been erased, thus leading to a seg fault. To
// remedy this, we keep the load to be removed by the trivial dead code
// elimination and we make sure to assign new virtual register definitions to
// its live operands to respect SSA.
makeDeadMI(*LoadOp, MRI);

return constrainSelectedInstRegOperands(*NewInstr.getInstr(), TII, TRI, RBI);
Expand Down Expand Up @@ -743,7 +742,14 @@ AIEBaseInstructionSelector::getCombinedOpcodeCONVLoad(
}

// Make an instruction trivially dead by creating and distributing new virtual
// registers to its defs
// registers to its defs.
// Erasing the load instruction breaks later on in the selection code. That is
// because we keep an iterator on erased instructions. This breaks while
// trying to eliminate a trivially dead instruction which requires access to
// its memory operands which have been erased, thus leading to a seg fault. To
// remedy this, we keep the load to be removed by the trivial dead code
// elimination and we make sure to assign a new virtual register definition to
// its live operands to respect SSA.
void AIEBaseInstructionSelector::makeDeadMI(MachineInstr &MI,
MachineRegisterInfo &MRI) {
if (MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) {
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Target/AIE/AIEBaseInstructionSelector.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
/// \file
Expand Down Expand Up @@ -96,6 +96,8 @@ class AIEBaseInstructionSelector : public InstructionSelector {
MachineInstr &EndI, MachineRegisterInfo &MRI,
Register CRReg, Register ValueReg,
unsigned DefaultCRVal = 0);
MachineInstrBuilder setCtrlRegister(MachineIRBuilder &MIB, Register CRReg,
unsigned Val);
AddressingModeInfo createAddressModeInfo(MachineInstr &MemI,
MachineOperand &SrcDstOp,
MachineOperand &PtrOp,
Expand Down
Loading