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[AIEX] Fix ExpandPostRAPseudos and PostSelectOptimize passes to satisfy MachineVerifier #349

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Feb 13, 2025
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[AIEX] Fix ExpandPostRAPseudos and PostSelectOptimize passes to satisfy MachineVerifier #349

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21340bb
[AIE2P] Remove undef operands from test inst-select-vconv-bfp16.mir
khallouh Feb 12, 2025
778c97c
[AIEX] Fix register flags in PostRAPseudoExpansion to satisfy Machine…
khallouh Feb 12, 2025
ed08029
[AIEX] Properly constrain addressing register classes in PostSelectOp…
khallouh Feb 12, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AIE/AIE2InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1039,7 +1039,7 @@ bool AIE2InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Register Src = MI.getOperand(1).getReg();
const unsigned MOVSclOpcode = getScalarMovOpcode(Dst, Src);
BuildMI(MBB, MI, DL, get(MOVSclOpcode), Dst)
.addReg(Src, getKillRegState(true));
.addReg(Src, getKillRegState(MI.getOperand(1).isKill()));
MI.eraseFromParent();
return true;
}
Expand Down
20 changes: 15 additions & 5 deletions llvm/lib/Target/AIE/AIEPostSelectOptimize.cpp
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Expand Up @@ -33,6 +33,7 @@
#include "AIE2.h"
#include "AIE2InstrInfo.h"
#include "AIE2RegisterInfo.h"
#include "AIEBaseRegisterBankInfo.h"
#include "AIEBaseRegisterInfo.h"
#include "AIECombinerHelper.h"
#include "Utils/AIELoopUtils.h"
Expand Down Expand Up @@ -364,7 +365,8 @@ static void collectIteratorComponentsUsage(
static bool tryToDuplicateLoadUse(
DenseMap<Register, SmallPtrSet<MachineInstr *, 8>> &LoadUses,
SmallSet<Register, 8> &NonLoadUses, MachineRegisterInfo &MRI,
const AIEBaseInstrInfo *TII) {
const AIEBaseInstrInfo *TII, const AIEBaseRegisterInfo *TRI,
const AIEBaseRegisterBankInfo *RBI) {

bool Changed = false;
for (auto &RegMILoad : LoadUses) {
Expand All @@ -381,9 +383,15 @@ static bool tryToDuplicateLoadUse(
// Here we cannot use COPY, because Machine CSE will run
// PerformTrivialCopyPropagation and our work will disappear.
// smoothly.
BuildMI(*DefReg->getParent(), ++InsertPoint, DefReg->getDebugLoc(),
TII->get(TII->getPseudoMoveOpcode()), DstReg)
.addReg(Reg);
MachineInstr *MI =
BuildMI(*DefReg->getParent(), ++InsertPoint, DefReg->getDebugLoc(),
TII->get(TII->getPseudoMoveOpcode()), DstReg)
.addReg(Reg);

// AIE's PseudoMove instruction takes compound register classes which
// contains registers of different sizes. We need to use the right classes
// to avoid the MachineVerifier complaining about mismatching sizes.
constrainSelectedInstRegOperands(*MI, *TII, *TRI, *RBI);

for (MachineInstr *UseMI : RegMILoad.second) {
for (auto &Operand : UseMI->operands()) {
Expand All @@ -407,6 +415,8 @@ bool duplicateAdressingRegs(MachineBasicBlock &MBB, MachineRegisterInfo &MRI) {
static_cast<const AIEBaseInstrInfo *>(ST.getInstrInfo());
const AIEBaseRegisterInfo *TRI =
static_cast<const AIEBaseRegisterInfo *>(ST.getRegisterInfo());
const AIEBaseRegisterBankInfo *RBI =
static_cast<const AIEBaseRegisterBankInfo *>(ST.getRegBankInfo());

assert(TII->getPseudoMoveOpcode() &&
"Target must have a PseudoMove instruction");
Expand Down Expand Up @@ -437,7 +447,7 @@ bool duplicateAdressingRegs(MachineBasicBlock &MBB, MachineRegisterInfo &MRI) {
// The second part, filter the real useful cases,
// registers used in both load and stores (or non load uses).
// Then duplicate those registers.
return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII);
return tryToDuplicateLoadUse(LoadUses, NonLoadUses, MRI, TII, TRI, RBI);
}

using Operation = AIEBaseInstrInfo::AbstractOp::OperationType;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp
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Expand Up @@ -1167,7 +1167,7 @@ bool AIE2PInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
BuildMI(MBB, MI, DL, get(AIE2P::MOV_alu_mv_mv_mv_scl), Dst)
.addReg(Src, getKillRegState(true));
.addReg(Src, getKillRegState(MI.getOperand(1).isKill()));
MI.eraseFromParent();
return true;
}
Expand Down
54 changes: 27 additions & 27 deletions llvm/test/CodeGen/AIE/aie2/GlobalISel/duplicate-iterators.mir
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Expand Up @@ -4,18 +4,18 @@
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates

# RUN: llc -mtriple aie2 -run-pass=aie-post-select-optimize %s -o - | FileCheck %s
# RUN: llc -mtriple aie2 -start-before=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2 -run-pass=aie-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple aie2 -start-before=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=POST-COALESCER
# RUN: llc -mtriple aie2 -start-after=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2 -start-after=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=COALESCER

# POST-COALESCER represents the case where we apply the post-select optimization and we
# stop after the coalescer. This case shows the optimized version.
# COALESCER represents the case where we don't apply the post-select optimization and we
# stop after the coalescer.
# stop after the coalescer.

---
name: two2d_descriptors
Expand All @@ -33,15 +33,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -77,7 +77,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm10_pseudo]].sub_dim_stride
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand All @@ -104,7 +104,7 @@ body: |
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm10_pseudo 14
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm10_pseudo 0
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -167,21 +167,21 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm10_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo3:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo4:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo5:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo6:%[0-9]+]]:edc = MOV_PD_imm10_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn = MOV_PD_imm10_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm10_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj = MOV_PD_imm10_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm10_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm10_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm10_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm10_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm10_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -225,7 +225,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_size
; POST-COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm10_pseudo]].sub_hi_dim_then_sub_dim_stride
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -260,7 +260,7 @@ body: |
; COALESCER-NEXT: undef [[MOV_PD_imm10_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm10_pseudo 0
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm10_pseudo 16
; COALESCER-NEXT: [[MOV_PD_imm10_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm10_pseudo 18
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AIE/aie2/postrapseudos/pseudoMove.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
# RUN: llc -verify-machineinstrs --march=aie2 -run-pass=postrapseudos %s -o - | FileCheck %s

---
Expand All @@ -13,7 +13,7 @@ alignment: 16
body: |
bb.0 (align 16):
; CHECK-LABEL: name: pseudoMov_GPR
; CHECK: $r1 = MOV_SCL_pseudo killed $r0
; CHECK: $r1 = MOV_SCL_pseudo $r0
$r1 = PseudoMove $r0
...

Expand All @@ -23,12 +23,12 @@ alignment: 16
body: |
bb.0 (align 16):
; CHECK-LABEL: name: pseudoMov_non_GPR
; CHECK: $r1 = MOV_mv_scl killed $p0
; CHECK-NEXT: $p0 = MOV_mv_scl killed $r1
; CHECK-NEXT: $p1 = MOV_mv_scl killed $p0
; CHECK-NEXT: $r1 = MOV_mv_scl killed $s0
; CHECK-NEXT: $s0 = MOV_mv_scl killed $r1
; CHECK-NEXT: $s1 = MOV_mv_scl killed $s0
; CHECK: $r1 = MOV_mv_scl $p0
; CHECK-NEXT: $p0 = MOV_mv_scl $r1
; CHECK-NEXT: $p1 = MOV_mv_scl $p0
; CHECK-NEXT: $r1 = MOV_mv_scl $s0
; CHECK-NEXT: $s0 = MOV_mv_scl $r1
; CHECK-NEXT: $s1 = MOV_mv_scl $s0
$r1 = PseudoMove $p0
$p0 = PseudoMove $r1
$p1 = PseudoMove $p0
Expand Down
52 changes: 26 additions & 26 deletions llvm/test/CodeGen/AIE/aie2p/GlobalIsel/duplicate-iterators.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates

# RUN: llc -mtriple aie2p -run-pass=aie-post-select-optimize %s -o - | FileCheck %s
# RUN: llc -mtriple aie2p -start-before=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2p -run-pass=aie-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple aie2p -start-before=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=POST-COALESCER
# RUN: llc -mtriple aie2p -start-after=aie-post-select-optimize -stop-after=register-coalescer \
# RUN: llc -mtriple aie2p -start-after=aie-post-select-optimize -stop-after=register-coalescer -verify-machineinstrs \
# RUN: %s -o - | FileCheck %s -check-prefix=COALESCER

# POST-COALESCER represents the case where we apply the post-select optimization and we
Expand All @@ -33,15 +33,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -77,7 +77,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_stride:ed = PseudoMove [[MOV_PD_imm11_pseudo]].sub_dim_stride
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand All @@ -104,7 +104,7 @@ body: |
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_stride:ed = MOV_PD_imm11_pseudo 14
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo1:%[0-9]+]].sub_dim_count:ed = MOV_PD_imm11_pseudo 0
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -167,21 +167,21 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:ep = COPY $p0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY $p1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:er = COPY $r0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 10
; CHECK-NEXT: [[PseudoMove:%[0-9]+]]:em_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo1:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 12
; CHECK-NEXT: [[PseudoMove1:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo1]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo2:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 14
; CHECK-NEXT: [[PseudoMove2:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo3:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo4:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo5:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo6:%[0-9]+]]:edc = MOV_PD_imm11_pseudo 0
; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn = MOV_PD_imm11_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn = PseudoMove [[MOV_PD_imm11_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj = MOV_PD_imm11_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj = PseudoMove [[MOV_PD_imm11_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo7:%[0-9]+]]:edn_as_32bit = MOV_PD_imm11_pseudo 16
; CHECK-NEXT: [[PseudoMove3:%[0-9]+]]:edn_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo7]]
; CHECK-NEXT: [[MOV_PD_imm11_pseudo8:%[0-9]+]]:edj_as_32bit = MOV_PD_imm11_pseudo 18
; CHECK-NEXT: [[PseudoMove4:%[0-9]+]]:edj_as_32bit = PseudoMove [[MOV_PD_imm11_pseudo8]]
; CHECK-NEXT: LoopStart [[COPY2]], 0
; CHECK-NEXT: PseudoJ_jump_imm %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
Expand Down Expand Up @@ -225,7 +225,7 @@ body: |
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_size
; POST-COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18
; POST-COALESCER-NEXT: [[PseudoMove:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = PseudoMove [[MOV_PD_imm11_pseudo]].sub_hi_dim_then_sub_dim_stride
; POST-COALESCER-NEXT: LoopStart [[COPY2]]
; POST-COALESCER-NEXT: LoopStart [[COPY2]], 0
; POST-COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; POST-COALESCER-NEXT: {{ $}}
; POST-COALESCER-NEXT: bb.1:
Expand Down Expand Up @@ -260,7 +260,7 @@ body: |
; COALESCER-NEXT: undef [[MOV_PD_imm11_pseudo2:%[0-9]+]].sub_hi_dim_then_sub_dim_count:eds = MOV_PD_imm11_pseudo 0
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_size:eds = MOV_PD_imm11_pseudo 16
; COALESCER-NEXT: [[MOV_PD_imm11_pseudo:%[0-9]+]].sub_hi_dim_then_sub_dim_stride:eds = MOV_PD_imm11_pseudo 18
; COALESCER-NEXT: LoopStart [[COPY2]]
; COALESCER-NEXT: LoopStart [[COPY2]], 0
; COALESCER-NEXT: PseudoJ_jump_imm %bb.1
; COALESCER-NEXT: {{ $}}
; COALESCER-NEXT: bb.1:
Expand Down
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