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[AIEX] Iterative feedback-driven post-pipeliner #359

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Feb 20, 2025
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3 changes: 3 additions & 0 deletions llvm/lib/Target/AIE/AIE2Subtarget.h
Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,9 @@ class AIE2Subtarget : public AIE2GenSubtargetInfo, public AIEBaseSubtarget {
StringRef FS, StringRef ABIName, const TargetMachine &TM);

bool enableMachineScheduler() const override { return true; }
bool enableMachinePipeliner() const override {
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Can we keep just the base implementation?

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Unfortunately AIEBaseSubTarget isn't actually a base class of AIE2Subtarget

return AIEBaseSubtarget::enableMachinePipeliner();
}
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CHECK: we just disable the pre-pipeliner, not the prescheduler. And 'forcing' assumes infinite willingness on the part of the postpipeliner.

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... but the prescheduler follows the pre-pipeliner

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Correct, I'll add a small comment

bool enablePostRAScheduler() const override { return true; }
bool enablePostRAMachineScheduler() const override { return true; }
bool forcePostRAScheduling() const override { return true; }
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9 changes: 9 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseSubtarget.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,11 @@ static cl::opt<unsigned> WAWStickyRegistersMemOpsThreshold(
cl::desc("Number of memory instructions to enable the register exclusion "
"heuristic in WAW sticky registers dep. removal"));

static cl::opt<bool> ForcePostPipeliner(
"aie-force-postpipeliner",
cl::desc(
"Force using AIE's post-pipeliner instead of the MachinePipeliner"),
cl::init(false), cl::Hidden);
// These are debugging/testing options.

// aie-latency-margin defines the latency that will be given to ExitSU edges.
Expand Down Expand Up @@ -848,3 +853,7 @@ AIEBaseSubtarget::getSMSMutationsImpl(const Triple &TT) {
}
return Mutations;
}

bool AIEBaseSubtarget::enableMachinePipeliner() const {
return !ForcePostPipeliner;
}
4 changes: 4 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseSubtarget.h
Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,10 @@ class AIEBaseSubtarget {
/// Required DAG mutations during software pipelining.
static std::vector<std::unique_ptr<ScheduleDAGMutation>>
getSMSMutationsImpl(const Triple &TT);

/// Whether to enable the pre-RA MachinePipeliner. This can be disabled to let
/// the post-RA pipeliner handle the scheduling.
bool enableMachinePipeliner() const;
};
} // namespace llvm

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10 changes: 7 additions & 3 deletions llvm/lib/Target/AIE/AIEMachineScheduler.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1079,9 +1079,13 @@ MachineBasicBlock *AIEPreRASchedStrategy::nextBlock() {
// The prescheduler also clutters the view of the postpipeliner, so we skip
// such blocks here.
auto Skip = [](MachineBasicBlock *Block) {
return PreSchedFollowsSkipPipeliner && Block &&
AIELoopUtils::isSingleMBBLoop(Block) &&
AIELoopUtils::getPipelinerDisabled(*Block);
if (!Block)
return false;
bool PrePipelinerDisabled =
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nit: const bool PrePipelinerDisabled

AIELoopUtils::getPipelinerDisabled(*Block) ||
!Block->getParent()->getSubtarget().enableMachinePipeliner();
return PreSchedFollowsSkipPipeliner &&
AIELoopUtils::isSingleMBBLoop(Block) && PrePipelinerDisabled;
};

do {
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