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andcarminati
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This work is intended to avoid 3D/3D (when possible) register spills.

The idea and rationale behind this work is in a previous Draft PR: #442.

To review, I recommend to follow this PR commit by commit.

Credits also for the co-author @krishnamtibrewala.

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andcarminati commented Oct 21, 2025

QoR results:

Core_Insn_Count Core_StackSize_absolute Core_PMSize_absolute

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Thanks you @andcarminati, very much !!

addPass(createGreedyRegisterAllocator(onlyAllocate3D2DRegisters));
addPass(createAIESuperRegRewriter());
if (EnableFineGrainedStagedRA)
addPass(createAIEUnallocatedSuperRegRewriter());
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Check : I think we should try the following, it should be helpful for onlyAllocate3D2DRegisters pass

    addPass(createGreedyRegisterAllocator(onlyAllocate3DRegisters));
    addPass(createAIESuperRegRewriter());
    if (EnableFineGrainedStagedRA)
      addPass(createAIEUnallocatedSuperRegRewriter());
    addPass(createGreedyRegisterAllocator(onlyAllocate3D2DRegisters));
    addPass(createAIESuperRegRewriter());
    if (EnableFineGrainedStagedRA)
      addPass(createAIEUnallocatedSuperRegRewriter());

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I would like to keeps as simple as possible now to setup a common ground first, and then we can test small changes to see the impact. I think it will better to decide.

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Also do you think following commit will help ?
a681b6e

andcarminati and others added 2 commits October 22, 2025 02:26
Now we filter by register class and usage. Basically, we exclude here
instructions like copies and non-2D/3D ones.

Co-Authored-By: Krishnam Tibrewala <[email protected]>
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Also do you think following commit will help ? a681b6e

Maybe yes! As mentioned before, I prefer to keep just the minimal necessary changes. We can test after, on top of this PR.

andcarminati and others added 6 commits October 22, 2025 02:35
If we don't need a full register, we can expand to individual lanes.

Co-Authored-By: Krishnam Tibrewala <[email protected]>
This avoids cycles in bundles that appear in VirtRegRewriter.
We also update LIs related to src and dst operands of those
expanded copies.

Co-Authored-By: Krishnam Tibrewala <[email protected]>
@andcarminati andcarminati force-pushed the andreu.extend.2d3d.allocation branch from 31b7e71 to a27561f Compare October 22, 2025 08:35
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2 participants