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Add channel unit-tests from jgmelber's mlir-air fork. #189

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Add channel unit-tests from jgmelber's mlir-air fork. #189

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18 changes: 18 additions & 0 deletions test/50_air_channel_move/00_worker2worker/aie.mlir
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module @aie.partition_0 {
%0 = AIE.tile(1, 1)
%1 = AIE.tile(1, 2)
%2 = AIE.objectFifo.createObjectFifo(%0, {%1}, 2) : !AIE.objectFifo<memref<32xi32, 2>>
%3 = AIE.core(%1) {
%5 = AIE.objectFifo.acquire<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%6 = AIE.objectFifo.subview.access %5[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
AIE.objectFifo.release<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
AIE.end
} {elf_file = "partition_0_core_1_2.elf"}
%4 = AIE.core(%0) {
%5 = AIE.objectFifo.acquire<Produce> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%6 = AIE.objectFifo.subview.access %5[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
AIE.objectFifo.release<Produce> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
AIE.end
} {elf_file = "partition_0_core_1_1.elf"}
}

26 changes: 26 additions & 0 deletions test/50_air_channel_move/00_worker2worker/air.mlir
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#set = affine_set<()[s0, s1] : (s0 >= 0, s1 == 0)>
#set1 = affine_set<()[s0, s1] : (s0 >= 0, s1 - 1 == 0)>
module {
air.channel @channel_0 [1, 1]
func.func @graph() {
%c2 = arith.constant 2 : index
%c1 = arith.constant 1 : index
air.herd @herd_0 tile (%arg0, %arg1) in (%arg2=%c1, %arg3=%c2) {
%c0 = arith.constant 0 : index
%c32 = arith.constant 32 : index
affine.if #set()[%arg0, %arg1] {
%alloc = memref.alloc() {sym_name = "scratch"} : memref<32xi32, 2>
air.channel.put @channel_0[] (%alloc[%c0] [%c32] [%c0]) : (memref<32xi32, 2>)
memref.dealloc %alloc : memref<32xi32, 2>
}
affine.if #set1()[%arg0, %arg1] {
%alloc = memref.alloc() {sym_name = "scratch_copy"} : memref<32xi32, 2>
air.channel.get @channel_0[] (%alloc[%c0] [%c32] [%c0]) : (memref<32xi32, 2>)
memref.dealloc %alloc : memref<32xi32, 2>
}
air.herd_terminator
}
return
}
}

20 changes: 20 additions & 0 deletions test/50_air_channel_move/01_one_tile/aie.mlir
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module @aie.partition_0 {
%0 = AIE.tile(1, 1)
%1 = AIE.tile(2, 0)
%2 = AIE.objectFifo.createObjectFifo(%1, {%0}, 1) : !AIE.objectFifo<memref<32xi32, 2>>
%3 = AIE.objectFifo.createObjectFifo(%0, {%1}, 1) : !AIE.objectFifo<memref<32xi32, 2>>
%4 = AIE.core(%0) {
%5 = AIE.objectFifo.acquire<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%6 = AIE.objectFifo.subview.access %5[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
%7 = AIE.objectFifo.acquire<Produce> (%3 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%8 = AIE.objectFifo.subview.access %7[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
affine.for %arg0 = 0 to 32 {
%9 = affine.load %6[%arg0] : memref<32xi32, 2>
affine.store %9, %8[%arg0] : memref<32xi32, 2>
}
AIE.objectFifo.release<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
AIE.objectFifo.release<Produce> (%3 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
AIE.end
} {elf_file = "partition_0_core_1_1.elf"}
}

22 changes: 22 additions & 0 deletions test/50_air_channel_move/01_one_tile/air.mlir
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module {
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<4096xi32>) {
%c1 = arith.constant 1 : index
air.herd @herd_0 tile (%arg2, %arg3) in (%arg4=%c1, %arg5=%c1) args(%arg6=%arg0, %arg7=%arg1) : memref<4096xi32>, memref<4096xi32> {
%c0 = arith.constant 0 : index
%c32 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "scratch"} : memref<32xi32, 2>
%alloc_0 = memref.alloc() {sym_name = "scratch_copy"} : memref<32xi32, 2>
air.dma_memcpy_nd (%alloc[%c0] [%c32] [%c0], %arg6[%c0] [%c32] [%c0]) {id = 1 : i32} : (memref<32xi32, 2>, memref<4096xi32>)
affine.for %arg8 = 0 to 32 {
%0 = affine.load %alloc[%arg8] : memref<32xi32, 2>
affine.store %0, %alloc_0[%arg8] : memref<32xi32, 2>
}
air.dma_memcpy_nd (%arg7[%c0] [%c32] [%c0], %alloc_0[%c0] [%c32] [%c0]) {id = 2 : i32} : (memref<4096xi32>, memref<32xi32, 2>)
memref.dealloc %alloc_0 : memref<32xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}

28 changes: 28 additions & 0 deletions test/50_air_channel_move/01_one_tile/channels.mlir
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module {
air.channel @channel_1 [1, 1]
air.channel @channel_0 [1, 1]
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<4096xi32>) {
%c32 = arith.constant 32 : index
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
air.channel.put @channel_0[] (%arg0[%c0] [%c32] [%c0]) : (memref<4096xi32>)
air.channel.get @channel_1[] (%arg1[%c0] [%c32] [%c0]) : (memref<4096xi32>)
air.herd @herd_0 tile (%arg2, %arg3) in (%arg4=%c1, %arg5=%c1) {
%c0_0 = arith.constant 0 : index
%c32_1 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "scratch"} : memref<32xi32, 2>
%alloc_2 = memref.alloc() {sym_name = "scratch_copy"} : memref<32xi32, 2>
air.channel.get @channel_0[] (%alloc[%c0_0] [%c32_1] [%c0_0]) : (memref<32xi32, 2>)
affine.for %arg6 = 0 to 32 {
%0 = affine.load %alloc[%arg6] : memref<32xi32, 2>
affine.store %0, %alloc_2[%arg6] : memref<32xi32, 2>
}
air.channel.put @channel_1[] (%alloc_2[%c0_0] [%c32_1] [%c0_0]) : (memref<32xi32, 2>)
memref.dealloc %alloc_2 : memref<32xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}

22 changes: 22 additions & 0 deletions test/50_air_channel_move/02_whole_vector/aie.mlir
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module @aie.partition_0 {
%0 = AIE.tile(1, 1)
%1 = AIE.tile(2, 0)
%2 = AIE.objectFifo.createObjectFifo(%1, {%0}, 1) : !AIE.objectFifo<memref<32xi32, 2>>
%3 = AIE.objectFifo.createObjectFifo(%0, {%1}, 1) : !AIE.objectFifo<memref<32xi32, 2>>
%4 = AIE.core(%0) {
affine.for %arg0 = 0 to 4096 step 32 {
%5 = AIE.objectFifo.acquire<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%6 = AIE.objectFifo.subview.access %5[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
%7 = AIE.objectFifo.acquire<Produce> (%3 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%8 = AIE.objectFifo.subview.access %7[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
affine.for %arg1 = 0 to 32 {
%9 = affine.load %6[%arg1] : memref<32xi32, 2>
affine.store %9, %8[%arg1] : memref<32xi32, 2>
}
AIE.objectFifo.release<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
AIE.objectFifo.release<Produce> (%3 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
}
AIE.end
} {elf_file = "partition_0_core_1_1.elf"}
}

23 changes: 23 additions & 0 deletions test/50_air_channel_move/02_whole_vector/air.mlir
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module {
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<4096xi32>) {
%c1 = arith.constant 1 : index
air.herd @herd_0 tile (%arg2, %arg3) in (%arg4=%c1, %arg5=%c1) args(%arg6=%arg0, %arg7=%arg1) : memref<4096xi32>, memref<4096xi32> {
%c0 = arith.constant 0 : index
%c32 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "scratch"} : memref<32xi32, 2>
%alloc_0 = memref.alloc() {sym_name = "scratch_copy"} : memref<32xi32, 2>
affine.for %arg8 = 0 to 4096 step 32 {
air.dma_memcpy_nd (%alloc[%c0] [%c32] [%c0], %arg6[%arg8] [%c32] [%c0]) {id = 1 : i32} : (memref<32xi32, 2>, memref<4096xi32>)
affine.for %arg9 = 0 to 32 {
%0 = affine.load %alloc[%arg9] : memref<32xi32, 2>
affine.store %0, %alloc_0[%arg9] : memref<32xi32, 2>
}
air.dma_memcpy_nd (%arg7[%arg8] [%c32] [%c0], %alloc_0[%c0] [%c32] [%c0]) {id = 2 : i32} : (memref<4096xi32>, memref<32xi32, 2>)
}
memref.dealloc %alloc_0 : memref<32xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}
34 changes: 34 additions & 0 deletions test/50_air_channel_move/02_whole_vector/channels.mlir
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module {
air.channel @channel_1 [1, 1]
air.channel @channel_0 [1, 1]
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<4096xi32>) {
%c32 = arith.constant 32 : index
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
affine.for %arg2 = 0 to 4096 step 32 {
air.channel.put @channel_0[] (%arg0[%arg2] [%c32] [%c0]) : (memref<4096xi32>)
}
affine.for %arg2 = 0 to 4096 step 32 {
air.channel.get @channel_1[] (%arg1[%arg2] [%c32] [%c0]) : (memref<4096xi32>)
}
air.herd @herd_0 tile (%arg2, %arg3) in (%arg4=%c1, %arg5=%c1) {
%c0_0 = arith.constant 0 : index
%c32_1 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "scratch"} : memref<32xi32, 2>
%alloc_2 = memref.alloc() {sym_name = "scratch_copy"} : memref<32xi32, 2>
affine.for %arg6 = 0 to 4096 step 32 {
air.channel.get @channel_0[] (%alloc[%c0_0] [%c32_1] [%c0_0]) : (memref<32xi32, 2>)
affine.for %arg7 = 0 to 32 {
%0 = affine.load %alloc[%arg7] : memref<32xi32, 2>
affine.store %0, %alloc_2[%arg7] : memref<32xi32, 2>
}
air.channel.put @channel_1[] (%alloc_2[%c0_0] [%c32_1] [%c0_0]) : (memref<32xi32, 2>)
}
memref.dealloc %alloc_2 : memref<32xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}

24 changes: 24 additions & 0 deletions test/50_air_channel_move/03_reduce/aie.mlir
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module @aie.partition_0 {
%0 = AIE.tile(1, 1)
%1 = AIE.tile(2, 0)
%2 = AIE.objectFifo.createObjectFifo(%1, {%0}, 1) : !AIE.objectFifo<memref<32xi32, 2>>
%3 = AIE.objectFifo.createObjectFifo(%0, {%1}, 1) : !AIE.objectFifo<memref<1xi32, 2>>
%4 = AIE.core(%0) {
%5 = AIE.objectFifo.acquire<Produce> (%3 : !AIE.objectFifo<memref<1xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<1xi32, 2>>
%6 = AIE.objectFifo.subview.access %5[0] : !AIE.objectFifoSubview<memref<1xi32, 2>> -> memref<1xi32, 2>
affine.for %arg0 = 0 to 4096 step 32 {
%7 = AIE.objectFifo.acquire<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%8 = AIE.objectFifo.subview.access %7[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
affine.for %arg1 = 0 to 32 {
%9 = affine.load %8[%arg1] : memref<32xi32, 2>
%10 = affine.load %6[0] : memref<1xi32, 2>
%11 = arith.addi %9, %10 : i32
affine.store %11, %6[0] : memref<1xi32, 2>
}
AIE.objectFifo.release<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
}
AIE.objectFifo.release<Produce> (%3 : !AIE.objectFifo<memref<1xi32, 2>>, 1)
AIE.end
} {elf_file = "partition_0_core_1_1.elf"}
}

27 changes: 27 additions & 0 deletions test/50_air_channel_move/03_reduce/air.mlir
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module {
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<1xi32>) {
%c1 = arith.constant 1 : index
air.herd @herd_0 tile (%arg2, %arg3) in (%arg4=%c1, %arg5=%c1) args(%arg6=%arg0, %arg7=%arg1) : memref<4096xi32>, memref<1xi32> {
%c0 = arith.constant 0 : index
%c1_0 = arith.constant 1 : index
%c32 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "scratch"} : memref<32xi32, 2>
%alloc_1 = memref.alloc() {sym_name = "scratch_copy"} : memref<1xi32, 2>
affine.for %arg8 = 0 to 4096 step 32 {
air.dma_memcpy_nd (%alloc[%c0] [%c32] [%c0], %arg6[%arg8] [%c32] [%c0]) {id = 1 : i32} : (memref<32xi32, 2>, memref<4096xi32>)
affine.for %arg9 = 0 to 32 {
%0 = affine.load %alloc[%arg9] : memref<32xi32, 2>
%1 = affine.load %alloc_1[0] : memref<1xi32, 2>
%2 = arith.addi %0, %1 : i32
affine.store %2, %alloc_1[0] : memref<1xi32, 2>
}
}
air.dma_memcpy_nd (%arg7[%c0] [%c1_0] [%c0], %alloc_1[%c0] [%c1_0] [%c0]) {id = 2 : i32} : (memref<1xi32>, memref<1xi32, 2>)
memref.dealloc %alloc_1 : memref<1xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}

35 changes: 35 additions & 0 deletions test/50_air_channel_move/03_reduce/channels.mlir
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module {
air.channel @channel_1 [1, 1]
air.channel @channel_0 [1, 1]
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<1xi32>) {
%c32 = arith.constant 32 : index
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
affine.for %arg2 = 0 to 4096 step 32 {
air.channel.put @channel_0[] (%arg0[%arg2] [%c32] [%c0]) : (memref<4096xi32>)
}
air.channel.get @channel_1[] (%arg1[%c0] [%c1] [%c0]) : (memref<1xi32>)
air.herd @herd_0 tile (%arg2, %arg3) in (%arg4=%c1, %arg5=%c1) {
%c0_0 = arith.constant 0 : index
%c1_1 = arith.constant 1 : index
%c32_2 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "scratch"} : memref<32xi32, 2>
%alloc_3 = memref.alloc() {sym_name = "scratch_copy"} : memref<1xi32, 2>
affine.for %arg6 = 0 to 4096 step 32 {
air.channel.get @channel_0[] (%alloc[%c0_0] [%c32_2] [%c0_0]) : (memref<32xi32, 2>)
affine.for %arg7 = 0 to 32 {
%0 = affine.load %alloc[%arg7] : memref<32xi32, 2>
%1 = affine.load %alloc_3[0] : memref<1xi32, 2>
%2 = arith.addi %0, %1 : i32
affine.store %2, %alloc_3[0] : memref<1xi32, 2>
}
}
air.channel.put @channel_1[] (%alloc_3[%c0_0] [%c1_1] [%c0_0]) : (memref<1xi32, 2>)
memref.dealloc %alloc_3 : memref<1xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}

28 changes: 28 additions & 0 deletions test/50_air_channel_move/04_two_inputs/aie.mlir
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module @aie.partition_0 {
%0 = AIE.tile(1, 1)
%1 = AIE.tile(2, 0)
%2 = AIE.objectFifo.createObjectFifo(%1, {%0}, 2) {sym_name = "inA_0_0"} : !AIE.objectFifo<memref<32xi32, 2>>
%3 = AIE.objectFifo.createObjectFifo(%1, {%0}, 2) {sym_name = "inB_0_0"} : !AIE.objectFifo<memref<32xi32, 2>>
%4 = AIE.objectFifo.createObjectFifo(%0, {%1}, 2) {sym_name = "outC_0_0"} : !AIE.objectFifo<memref<32xi32, 2>>
%5 = AIE.core(%0) {
affine.for %arg0 = 0 to 4096 step 32 {
%6 = AIE.objectFifo.acquire<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%7 = AIE.objectFifo.subview.access %6[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
%8 = AIE.objectFifo.acquire<Consume> (%3 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%9 = AIE.objectFifo.subview.access %8[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
%10 = AIE.objectFifo.acquire<Produce> (%4 : !AIE.objectFifo<memref<32xi32, 2>>, 1) : !AIE.objectFifoSubview<memref<32xi32, 2>>
%11 = AIE.objectFifo.subview.access %10[0] : !AIE.objectFifoSubview<memref<32xi32, 2>> -> memref<32xi32, 2>
affine.for %arg1 = 0 to 32 {
%12 = affine.load %7[%arg1] : memref<32xi32, 2>
%13 = affine.load %9[%arg1] : memref<32xi32, 2>
%14 = arith.addi %13, %12 : i32
affine.store %14, %11[%arg1] : memref<32xi32, 2>
}
AIE.objectFifo.release<Consume> (%2 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
AIE.objectFifo.release<Consume> (%3 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
AIE.objectFifo.release<Produce> (%4 : !AIE.objectFifo<memref<32xi32, 2>>, 1)
}
AIE.end
} {elf_file = "partition_0_core_1_1.elf"}
}

29 changes: 29 additions & 0 deletions test/50_air_channel_move/04_two_inputs/air.mlir
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module {
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<4096xi32>, %arg2: memref<4096xi32>) {
%c1 = arith.constant 1 : index
air.herd @herd_0 tile (%arg3, %arg4) in (%arg5=%c1, %arg6=%c1) args(%arg7=%arg0, %arg8=%arg1, %arg9=%arg2) : memref<4096xi32>, memref<4096xi32>, memref<4096xi32> {
%c0 = arith.constant 0 : index
%c32 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "inA"} : memref<32xi32, 2>
%alloc_0 = memref.alloc() {sym_name = "inB"} : memref<32xi32, 2>
%alloc_1 = memref.alloc() {sym_name = "outC"} : memref<32xi32, 2>
affine.for %arg10 = 0 to 4096 step 32 {
air.dma_memcpy_nd (%alloc[%c0] [%c32] [%c0], %arg7[%arg10] [%c32] [%c0]) {id = 1 : i32} : (memref<32xi32, 2>, memref<4096xi32>)
air.dma_memcpy_nd (%alloc_0[%c0] [%c32] [%c0], %arg8[%arg10] [%c32] [%c0]) {id = 1 : i32} : (memref<32xi32, 2>, memref<4096xi32>)
affine.for %arg11 = 0 to 32 {
%0 = affine.load %alloc[%arg11] : memref<32xi32, 2>
%1 = affine.load %alloc_0[%arg11] : memref<32xi32, 2>
%2 = arith.addi %1, %0 : i32
affine.store %2, %alloc_1[%arg11] : memref<32xi32, 2>
}
air.dma_memcpy_nd (%arg9[%arg10] [%c32] [%c0], %alloc_1[%c0] [%c32] [%c0]) {id = 2 : i32} : (memref<4096xi32>, memref<32xi32, 2>)
}
memref.dealloc %alloc_1 : memref<32xi32, 2>
memref.dealloc %alloc_0 : memref<32xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}

43 changes: 43 additions & 0 deletions test/50_air_channel_move/04_two_inputs/channels.mlir
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Original file line number Diff line number Diff line change
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module {
air.channel @channel_2 [1, 1]
air.channel @channel_1 [1, 1]
air.channel @channel_0 [1, 1]
func.func @graph(%arg0: memref<4096xi32>, %arg1: memref<4096xi32>, %arg2: memref<4096xi32>) {
%c32 = arith.constant 32 : index
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
affine.for %arg3 = 0 to 4096 step 32 {
air.channel.put @channel_0[] (%arg0[%arg3] [%c32] [%c0]) : (memref<4096xi32>)
}
affine.for %arg3 = 0 to 4096 step 32 {
air.channel.put @channel_1[] (%arg1[%arg3] [%c32] [%c0]) : (memref<4096xi32>)
}
affine.for %arg3 = 0 to 4096 step 32 {
air.channel.get @channel_2[] (%arg2[%arg3] [%c32] [%c0]) : (memref<4096xi32>)
}
air.herd @herd_0 tile (%arg3, %arg4) in (%arg5=%c1, %arg6=%c1) {
%c0_0 = arith.constant 0 : index
%c32_1 = arith.constant 32 : index
%alloc = memref.alloc() {sym_name = "inA"} : memref<32xi32, 2>
%alloc_2 = memref.alloc() {sym_name = "inB"} : memref<32xi32, 2>
%alloc_3 = memref.alloc() {sym_name = "outC"} : memref<32xi32, 2>
affine.for %arg7 = 0 to 4096 step 32 {
air.channel.get @channel_0[] (%alloc[%c0_0] [%c32_1] [%c0_0]) : (memref<32xi32, 2>)
air.channel.get @channel_1[] (%alloc_2[%c0_0] [%c32_1] [%c0_0]) : (memref<32xi32, 2>)
affine.for %arg8 = 0 to 32 {
%0 = affine.load %alloc[%arg8] : memref<32xi32, 2>
%1 = affine.load %alloc_2[%arg8] : memref<32xi32, 2>
%2 = arith.addi %1, %0 : i32
affine.store %2, %alloc_3[%arg8] : memref<32xi32, 2>
}
air.channel.put @channel_2[] (%alloc_3[%c0_0] [%c32_1] [%c0_0]) : (memref<32xi32, 2>)
}
memref.dealloc %alloc_3 : memref<32xi32, 2>
memref.dealloc %alloc_2 : memref<32xi32, 2>
memref.dealloc %alloc : memref<32xi32, 2>
air.herd_terminator
}
return
}
}

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