Build: (bc45bf0) Added PG344 Design Considerations

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diff --git a/...ocs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.doctree b/...ocs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.doctree
diff --git a/pciedebug/build/doctrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/index.doctree b/pciedebug/build/doctrees/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/index.doctree
diff --git a/pciedebug/build/doctrees/environment.pickle b/pciedebug/build/doctrees/environment.pickle
diff --git a/...ubsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst.txt b/...ubsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.rst.txt
@@ -0,0 +1,61 @@
+.. _PG302_important_design_considerations:
+
+
+Important Design Considerations from PG302
+==========================================
+
+.. container:: Introduction
+
+    When tackling design issues, navigating a lengthy product guide can be overwhelming. To streamline your troubleshooting process, this article lists essential design considerations directly from the product guide, highlighting key points to keep in mind. This article condenses over 200 pages into a focused, 10-12 page summary, making it easier to access the most relevant information quickly. For full details, be sure to click the provided link to explore each consideration further in the original product guide.
+
+.. note::
+   :class: highlight-box
+
+   **Link**: `Resets <https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Resets?tocId=h1v7mXtUbwccVJ7YmHm9Jg>`_
+
+   - If your board is designed to use the same PCIe edge connectors to operate with CPM and PL PCIE, then AMD recommend using PS reset using the Control Interface and Processing System (CIPS) IP core.
+
+.. note::
+   :class: highlight-box
+
+   **Link**: `Descriptor Engine <https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Descriptor-Engine?tocId=zPLzp4_2KsOEq1OQBKu9mA>`_
+
+   - The descriptor engine will have only one DMA read outstanding per queue at a time and can read as many descriptors as can fit in a queue is associated with interrupt aggregation, AMD recommends that the status descriptor be turned off, and instead the DMA status be received from the interrupt aggregation ring.
+
+.. note::
+   :class: highlight-box
+
+   **Link**: `H2C Stream Engine <https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/H2C-Stream-Engine?tocId=8B1g_MoJi9B~JYNKl5PE8w>`_
+
+   - The total length of all descriptors put together must be less than 64 KB.
+   - A packet with multiple descriptors straddling is not allowed due to the lack of per queue storage.
+
+.. note::
+   :class: highlight-box
+
+   **Link**: `C2H Stream Engine <https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/C2H-Stream-Engine?tocId=kLLbtbEfgONrsb5bysKeHQ>`_
+
+   - In Simple Bypass Mode, the engine does not track anything for the queue, and the user logic can define its own method to receive descriptors. The user logic is then responsible for delivering the packet and associated descriptor through the simple bypass interface.
+   - The ordering of the descriptors fetched by a queue in the bypass interface and the C2H stream interface must be maintained across all queues in bypass mode.
+
+.. note::
+   :class: highlight-box
+
+   **Link**: `AXI Memory Mapped Bridge Master Interface <https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Memory-Mapped-Bridge-Master-Interface>`_
+
+   - The AXI MM Bridge Master interface is used for high bandwidth access to AXI Memory Mapped space from the host. The interface supports up to 32 outstanding AXI reads and writes. One or more PCIe BAR of any physical function (PF) or virtual function (VF) can be mapped to the AXI-MM bridge master interface. This selection must be made prior to design compilation.
+   - Note that all VFs belonging to the same PF share the same PCIe to AXI translation vector. Therefore, the AXI address space of each VF is concatenated together. Use VFG_OFFSET to calculate the actual starting address of AXI for a particular VF.
+
+.. note::
+   :class: highlight-box
+
+   **Link**: `AXI Memory Mapped Bridge Slave Interface <https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Memory-Mapped-Bridge-Slave-Interface>`_
+
+   - The AXI-MM Bridge Slave interface is used for high bandwidth memory transfers between the user logic and the Host. AXI to PCIe translation is supported through the AXI to PCIe BARs. The interface will split requests as necessary to obey PCIe MPS and 4 KB boundary crossing requirements. Up to 32 outstanding read and write requests are supported.
+
+.. note::
+   :class: highlight-box
+
+   **Link**: `Interrupt Module <https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Interrupt-Module>`_
+
+   - Queue-based interrupts and user interrupts are allowed on PFs and VFs, but error interrupts are allowed only on PFs.
diff --git a/.../build/html/_sources/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/index.rst.txt b/.../build/html/_sources/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/index.rst.txt
@@ -11,6 +11,7 @@ QDMA Subsystem for PCIExpress (IP/Driver)
     debug_faq.rst
     links_docs_misc.rst
     PG302_important_design_considerations.rst
+	PG344_important_design_considerations.rst
 
 
 

diff --git a/...l/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.html b/...l/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/PG344_important_design_considerations.html
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+  <div class="section" id="important-design-considerations-from-pg302">
+<span id="pg302-important-design-considerations"></span><h1>Important Design Considerations from PG302<a class="headerlink" href="#important-design-considerations-from-pg302" title="Permalink to this heading">¶</a></h1>
+<div class="introduction docutils container">
+<p>When tackling design issues, navigating a lengthy product guide can be overwhelming. To streamline your troubleshooting process, this article lists essential design considerations directly from the product guide, highlighting key points to keep in mind. This article condenses over 200 pages into a focused, 10-12 page summary, making it easier to access the most relevant information quickly. For full details, be sure to click the provided link to explore each consideration further in the original product guide.</p>
+</div>
+<div class="highlight-box admonition note">
+<p class="admonition-title">Note</p>
+<p><strong>Link</strong>: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Resets?tocId=h1v7mXtUbwccVJ7YmHm9Jg">Resets</a></p>
+<ul class="simple">
+<li><p>If your board is designed to use the same PCIe edge connectors to operate with CPM and PL PCIE, then AMD recommend using PS reset using the Control Interface and Processing System (CIPS) IP core.</p></li>
+</ul>
+</div>
+<div class="highlight-box admonition note">
+<p class="admonition-title">Note</p>
+<p><strong>Link</strong>: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Descriptor-Engine?tocId=zPLzp4_2KsOEq1OQBKu9mA">Descriptor Engine</a></p>
+<ul class="simple">
+<li><p>The descriptor engine will have only one DMA read outstanding per queue at a time and can read as many descriptors as can fit in a queue is associated with interrupt aggregation, AMD recommends that the status descriptor be turned off, and instead the DMA status be received from the interrupt aggregation ring.</p></li>
+</ul>
+</div>
+<div class="highlight-box admonition note">
+<p class="admonition-title">Note</p>
+<p><strong>Link</strong>: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/H2C-Stream-Engine?tocId=8B1g_MoJi9B~JYNKl5PE8w">H2C Stream Engine</a></p>
+<ul class="simple">
+<li><p>The total length of all descriptors put together must be less than 64 KB.</p></li>
+<li><p>A packet with multiple descriptors straddling is not allowed due to the lack of per queue storage.</p></li>
+</ul>
+</div>
+<div class="highlight-box admonition note">
+<p class="admonition-title">Note</p>
+<p><strong>Link</strong>: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/C2H-Stream-Engine?tocId=kLLbtbEfgONrsb5bysKeHQ">C2H Stream Engine</a></p>
+<ul class="simple">
+<li><p>In Simple Bypass Mode, the engine does not track anything for the queue, and the user logic can define its own method to receive descriptors. The user logic is then responsible for delivering the packet and associated descriptor through the simple bypass interface.</p></li>
+<li><p>The ordering of the descriptors fetched by a queue in the bypass interface and the C2H stream interface must be maintained across all queues in bypass mode.</p></li>
+</ul>
+</div>
+<div class="highlight-box admonition note">
+<p class="admonition-title">Note</p>
+<p><strong>Link</strong>: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Memory-Mapped-Bridge-Master-Interface">AXI Memory Mapped Bridge Master Interface</a></p>
+<ul class="simple">
+<li><p>The AXI MM Bridge Master interface is used for high bandwidth access to AXI Memory Mapped space from the host. The interface supports up to 32 outstanding AXI reads and writes. One or more PCIe BAR of any physical function (PF) or virtual function (VF) can be mapped to the AXI-MM bridge master interface. This selection must be made prior to design compilation.</p></li>
+<li><p>Note that all VFs belonging to the same PF share the same PCIe to AXI translation vector. Therefore, the AXI address space of each VF is concatenated together. Use VFG_OFFSET to calculate the actual starting address of AXI for a particular VF.</p></li>
+</ul>
+</div>
+<div class="highlight-box admonition note">
+<p class="admonition-title">Note</p>
+<p><strong>Link</strong>: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Memory-Mapped-Bridge-Slave-Interface">AXI Memory Mapped Bridge Slave Interface</a></p>
+<ul class="simple">
+<li><p>The AXI-MM Bridge Slave interface is used for high bandwidth memory transfers between the user logic and the Host. AXI to PCIe translation is supported through the AXI to PCIe BARs. The interface will split requests as necessary to obey PCIe MPS and 4 KB boundary crossing requirements. Up to 32 outstanding read and write requests are supported.</p></li>
+</ul>
+</div>
+<div class="highlight-box admonition note">
+<p class="admonition-title">Note</p>
+<p><strong>Link</strong>: <a class="reference external" href="https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Interrupt-Module">Interrupt Module</a></p>
+<ul class="simple">
+<li><p>Queue-based interrupts and user interrupts are allowed on PFs and VFs, but error interrupts are allowed only on PFs.</p></li>
+</ul>
+</div>
+</div>
+
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