Maintain port ordering for functional backend

[KrystalDelusion]

What are the reasons/motivation for this change?

As per #5128 (comment),

read_verilog << EOF
module top (A, C, B, X, Z, Y);

input A, C, B;
output X, Z, Y;

assign X = C;
assign Y = B;
assign Z = A;

endmodule
EOF
hierarchy
opt_clean
write_functional_rosette

returns ports in reverse alphabetical order:

(struct top_Inputs (C B A) #:transparent
  ; C (bitvector 1)
  ; B (bitvector 1)
  ; A (bitvector 1)
)
(struct top_Outputs (Z Y X) #:transparent
  ; Z (bitvector 1)
  ; Y (bitvector 1)
  ; X (bitvector 1)
)

(without the opt_clean then the order is the same as input).

Explain how this is achieved.

1. Use module->ports instead of module->wires() to get the ordered list of ports.
2. Use reverse iterators to compensate for hashlib::dict iterating backwards.

If applicable, please suggest to reviewers how they can test the change.