GitHub - Youva/VHDL: Projets en code VHDL

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Processeur		Processeur
SHA256		SHA256
compile		compile
log		log
src		src
Edfmap.ini		Edfmap.ini
SHA256.adf		SHA256.adf
SHA256.aws		SHA256.aws
SHA256.wsw		SHA256.wsw
bde.set		bde.set
compilation.order		compilation.order
compile.cfg		compile.cfg
library.cfg		library.cfg
projlib.cfg		projlib.cfg
sha256.wsp		sha256.wsp
synthesis.order		synthesis.order