GitHub - abagali1/R10K-Processor: Advanced R10K-based Out-of-Order Pipelined Processor in SystemVerilog

abagali1 / R10K-Processor Public

Advanced R10K-based Out-of-Order Pipelined Processor in SystemVerilog

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Name		Name	Last commit message	Last commit date
Latest commit History 526 Commits
.vscode		.vscode
correct_out		correct_out
programs		programs
synth		synth
test		test
verilog		verilog
.gitignore		.gitignore
Makefile		Makefile
cpu.rep		cpu.rep
dft_diff.txt		dft_diff.txt
initialnovas.rc		initialnovas.rc
run_programs.py		run_programs.py
working.sh		working.sh
working_c.sh		working_c.sh