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Testbenches for i2c in #13

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904c6dc
saving
Kreijstal Jun 28, 2024
c5722a2
Refactored I2C PHY module for improved readability and maintainability.
Kreijstal Jun 28, 2024
da896a2
Set default value for `phy_busy` and update delay register width to 1…
Kreijstal Jun 28, 2024
ba5610b
creating testbench
Kreijstal Jun 28, 2024
606625c
free formatting
Kreijstal Jun 29, 2024
7c6feaa
formatting plus testbench works now
Kreijstal Jun 29, 2024
6cae407
compartementalize the test
Kreijstal Jun 29, 2024
3c0e001
save whatever
Kreijstal Jun 29, 2024
77303b7
looks good
Kreijstal Jun 29, 2024
442ff55
good progress
Kreijstal Jun 29, 2024
e6691ad
Refactored register assignments and state transitions in i2c_single_r…
Kreijstal Jun 30, 2024
af1280d
Updated state values to 5 bits in i2c_single_reg module.
Kreijstal Jun 30, 2024
9fd5aa9
It now works with verilator
Kreijstal Jun 30, 2024
fa5d025
some changes
Kreijstal Jun 30, 2024
bafe0a7
making everything a task
Kreijstal Jun 30, 2024
def7b23
making everything a task
Kreijstal Jun 30, 2024
e55ce7f
Updated state parameters and added padding bits to the input filters.
Kreijstal Jun 30, 2024
42ee37a
Added signal declarations and updated signal assignments for I2C slav…
Kreijstal Jun 30, 2024
657fbdc
generated blocks work
Kreijstal Jun 30, 2024
df1c388
verible format called everywhere
Kreijstal Jun 30, 2024
533aa0d
verilator bug
Kreijstal Jun 30, 2024
a6135c3
Fixing issue thanks to verilator
Kreijstal Jun 30, 2024
7d6d4c6
formatting using verilog format
Kreijstal Jun 30, 2024
7b8cd68
forgot to format
Kreijstal Jun 30, 2024
a753beb
this will fix rst so it is async
Kreijstal Jun 30, 2024
2545a6e
adding write event
Kreijstal Jul 2, 2024
b31fcfe
testbench goes on tb
Kreijstal Jul 2, 2024
1f52d3d
add this from other branch
Kreijstal Jul 2, 2024
6d0acaf
Merge pull request #1 from Kreijstal/last_write_event
Kreijstal Jul 2, 2024
974ae1c
fixing the test
Kreijstal Jul 2, 2024
67ad173
missing comma
Kreijstal Jul 2, 2024
019a642
fix the error of 0 sized int
Kreijstal Jul 2, 2024
e9e408a
changing testbenches, on NACK simply stop.. no need to go further...
Kreijstal Jul 8, 2024
4f0ac9a
let's stick to verilog for now
Kreijstal Jul 8, 2024
9b24b7d
changing logic a little bit
Kreijstal Jul 9, 2024
3541490
Initialize module registers with default values.
Kreijstal Jul 9, 2024
83d7df9
Initialized all state, address, data, mode, bit count, and signal reg…
Kreijstal Jul 9, 2024
338ce59
changing testbench
Kreijstal Jul 9, 2024
79bd7f0
fixing bug
Kreijstal Jul 9, 2024
bf545bc
fix master
Kreijstal Jul 9, 2024
6968834
adding parameter debug
Kreijstal Jul 12, 2024
14a8648
explicit debug statement
Kreijstal Jul 12, 2024
72fc6bc
negative reset
Kreijstal Jul 13, 2024
7688744
make conditionally verbose, otherwise, too verbose!
Kreijstal Jul 13, 2024
13bfbdc
verilog does not support implicit params for synth
Kreijstal Jul 13, 2024
2052790
fixing 1 display
Kreijstal Jul 15, 2024
3f82945
move from one place to the next
Kreijstal Jul 15, 2024
3fef99f
format using verilible
Kreijstal Jul 15, 2024
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25 changes: 25 additions & 0 deletions .github/workflows/icarus.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
name: Icarus Verilog CI

on:
push:
branches: [ "*" ]
pull_request:
branches: [ "*" ]

jobs:
build-and-test:
runs-on: ubuntu-latest

steps:
- uses: actions/checkout@v4

- name: Install dependencies
run: |
sudo apt-get update
sudo apt-get install -y iverilog verilator

- name: Compile with Icarus Verilog
run: iverilog -o sim_output -y rtl tb/i2c_master_tb.v

- name: Run simulation
run: ./sim_output
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -4,3 +4,4 @@
*.vvp
*.kate-swp

.aider*
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