arch/mcx-nxxx: Add support for NXP MCX-N236 CPU

This adds minimal support for NXP MCX-N236 CPU. Peripherals supported are:
- GPIO
- PINMUX
- CLOCK
- LPUART

An example board, FRDM-MCXN236 is also added, with a basic profile that
boots into nsh.

arch/arm/Kconfig

@@ -354,6 +354,14 @@ config ARCH_CHIP_NUC1XX
 	---help---
 		Nuvoton NUC100/120 architectures (ARM Cortex-M0).
 
+config ARCH_CHIP_MCX_NXXX
+	bool "NXP MCX NXXx Cortex-M33"
+	select ARCH_CORTEXM33
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DFPU
+	---help---
+		NXXx architectures (Cortex-M33)
+
 config ARCH_CHIP_RP2040
 	bool "Raspberry Pi RP2040"
 	select ARCH_CORTEXM0
@@ -1186,6 +1194,7 @@ config ARCH_CHIP
 	default "at32"		if ARCH_CHIP_AT32
 	default "cxd32xx"	if ARCH_CHIP_CXD32XX
 	default "csk6"		if ARCH_CHIP_CSK6
+	default "mcx-nxxx"	if ARCH_CHIP_MCX_NXXX
 
 config ARM_THUMB
 	bool "Thumb Mode"
@@ -1696,4 +1705,7 @@ endif
 if ARCH_CHIP_CXD32XX
 source "arch/arm/src/cxd32xx/Kconfig"
 endif
+if ARCH_CHIP_MCX_NXXX
+source "arch/arm/src/mcx-nxxx/Kconfig"
+endif
 endif # ARCH_ARM

arch/arm/include/mcx-nxxx/chip.h

@@ -0,0 +1,60 @@
+/****************************************************************************
+ * arch/arm/include/mcx-nxxx/chip.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_MCX_NXXX_CHIP_H
+#define __ARCH_ARM_INCLUDE_MCX_NXXX_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Cache line sizes (in bytes) for the MCX_NXXX (Cortex-M33). MCX_NXXX has
+ * two caches; LPCACHE which is the instruction cache, and CACHE64 which is
+ * for FlexSPI (Not present on n23x-series).
+ *
+ * There is no generic data cache.
+ */
+
+#define ARMV8M_ICACHE_LINESIZE 16  /* 16 bytes (4 words, Cortex-M33 only) */
+#define ARMV8M_DCACHE_LINESIZE 32  /* 32 bytes (8 words, FlexSPI only) */
+
+/* NVIC priority levels *****************************************************/
+
+/* Each priority field holds an 8-bit priority value, 0-15. The lower the
+ * value, the greater the priority of the corresponding interrupt. nx94x uses
+ * msbits [7:5] for priority and the rest are reserved.
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN        0xe0 /* E0h is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT    0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX        0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP       0x20 /* Step is the 5th bit */
+
+#define NXXX_GPIO_NPORTS              6
+
+#endif /* __ARCH_ARM_INCLUDE_MCX_NXXX_CHIP_H */

arch/arm/include/mcx-nxxx/irq.h

@@ -0,0 +1,72 @@
+/****************************************************************************
+ * arch/arm/include/mcx-nxxx/irq.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_MCX_NXXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_MCX_NXXX_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_N236)
+#  include <arch/mcx-nxxx/n236_irq.h>
+#else
+#  error "Unrecognized MCX-NXXx architecture"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC.  This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ */
+
+/* Common Processor Exceptions (vectors 0-15) */
+
+#define NXXX_IRQ_RESERVED       (0) /* Vector  0: Reset stack pointer value */
+                                    /* Vector  1: Reset(not handled by IRQ) */
+#define NXXX_IRQ_NMI            (2) /* Vector  2: Non-Maskable Int (NMI) */
+#define NXXX_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
+#define NXXX_IRQ_MEMFAULT       (4) /* Vector  4: MemManage fault */
+#define NXXX_IRQ_BUSFAULT       (5) /* Vector  5: Bus fault */
+#define NXXX_IRQ_USAGEFAULT     (6) /* Vector  6: Usage fault */
+#define NXXX_IRQ_USAGEFAULT     (6) /* Vector  7: Secure fault */
+                                    /* Vectors 8-10: Reserved */
+#define NXXX_IRQ_SVCALL        (11) /* Vector 11: Supervisor Call (SVC) */
+#define NXXX_IRQ_DBGMONITOR    (12) /* Vector 12: Debug Monitor */
+                                    /* Vector 13: Reserved */
+#define NXXX_IRQ_PENDSV        (14) /* Vector 14: Pendable System Service Request */
+#define NXXX_IRQ_SYSTICK       (15) /* Vector 15: System tick */
+
+/* Chip-Specific External interrupts */
+
+#define NXXX_IRQ_EXTINT        (16) /* Vector number of the first external interrupt*/
+
+#endif /* __ARCH_ARM_INCLUDE_MCX_NXXX_IRQ_H */