Pick up vector length from 'zvlXXXb' (RVV) mattr for riscv #17641

cbalint13 · 2025-02-11T09:41:17Z

This PR is an enhancement for #17631.

New functionality:

This also parses optional 'zvlXXXb' attribute from -mattr arguments, if user would supply such.

Enhanchements:

Separate GetVectorWidth() @LLVMTargetInfo a shared public function, reachable from python side too.
A basic codegen testcase for riscv{32,64} targets is introduced, for now it checks RVV presence/absence.
A target parser testcase for riscv{32,64} is also introduced, it checks sanity and VLEN relations.

This not alter any behavior except riscv targets.
This work here is a preliminary before enable TVM's SVE for riscv too.

tqchen · 2025-02-11T17:56:58Z

tests/python/codegen/test_target_codegen_riscv.py

+            name="C",
+        )
+        s = te.create_schedule(C.op)
+        s[C].vectorize(s[C].op.axis[0])


we are moving away from te schedule very soon, so let us instead use tir schedule

Reworked, it is even more simple now, I was expecting relay to go, not realizing the same about te.

cbalint13 · 2025-02-12T21:55:12Z

This is ready for review.
Cc (LLVM folks) @quic-sanirudh , @srkreddy1238

cbalint13 force-pushed the riscv-vectorwidth branch 6 times, most recently from 4a1912a to 2b186e9 Compare February 11, 2025 13:44

tqchen reviewed Feb 11, 2025

View reviewed changes

cbalint13 force-pushed the riscv-vectorwidth branch 6 times, most recently from 8a49899 to 146157d Compare February 12, 2025 01:57

cbalint13 marked this pull request as ready for review February 12, 2025 02:03

Pick up vector length from 'zvlXXXb' (RVV) mattr for riscv

4223771

cbalint13 force-pushed the riscv-vectorwidth branch from 146157d to 4223771 Compare February 12, 2025 09:16

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