Synthesis

Codes/ALU.v

@@ -9,19 +9,36 @@ module ALU (
     input carry_in;
     input [3:0] exe_cmd;
     output [3:0] status_bits;
-    output [31:0] result;
+    output reg [31:0] result;
 
-    wire N, Z, C, V;
-    assign {C, result} = (exe_cmd == 4'b0001) ? (in2) :  //MOV
-                         (exe_cmd == 4'b1001) ? (~in2) : //MVN
-                         (exe_cmd == 4'b0010) ? (in1 + in2) :    //ADD, LDR, STR
-                         (exe_cmd == 4'b0011) ? (in1 + in2 + carry_in) : //ADC
-                         (exe_cmd == 4'b0100) ? (in1 - in2) :    //SUB, CMP
-                         (exe_cmd == 4'b0101) ? (in1 - in2 - {31'b0, ~carry_in}) :    //SBC
-                         (exe_cmd == 4'b0110) ? (in1 & in2) :    //AND, TST
-                         (exe_cmd == 4'b0111) ? (in1 | in2) :    //ORR
-                         (exe_cmd == 4'b1000) ? (in1 ^ in2) :    //EOR
-                          33'b0;    //B
+    wire N, Z, V;
+    reg C;
+    wire [32:0] x1,x2,x3,x4,x5,x6,x7,x8,x9;
+
+    always @(exe_cmd, in1, in2, carry_in) begin
+        case(exe_cmd)
+            4'b0101: {C, result} = x1;    //SBC
+            4'b0011: {C, result} = x2;    //ADC
+            4'b0010: {C, result} = x3;    //ADD, LDR, STR
+            4'b0100: {C, result} = x4;    //SUB, CMP
+            4'b0110: {C, result} = x5;    //AND, TST
+            4'b0111: {C, result} = x6;    //ORR
+            4'b1000: {C, result} = x7;    //EOR
+            4'b1001: {C, result} = x8;    //MVN
+            4'b0001: {C, result} = x9;    //MOV
+            default: {C, result} = 32'b0;
+        endcase
+    end
+
+    assign x1 = (in1 - in2 - {31'b0, ~carry_in});
+    assign x2 = (in1 + in2 + carry_in);
+    assign x3 = (in1 + in2);
+    assign x4 = (in1 - in2);
+    assign x5 = (in1 & in2);
+    assign x6 = (in1 | in2);
+    assign x7 = (in1 ^ in2);
+    assign x8 = (~in2);
+    assign x9 = (in2);
 
     assign N = result[31];
     assign Z = (result == 32'b0) ? 1'b1 : 1'b0;

Codes/ARM.v

@@ -301,13 +301,22 @@ input          TD_CLK27;            //	TV Decoder 27MHz CLK
 ////////////////////////	GPIO	////////////////////////////////
 inout	[35:0]	GPIO_0;					//	GPIO Connection 0
 inout	[35:0]	GPIO_1;					//	GPIO Connection 1
-
+reg clock;
 	ARM_cpu CPU (
-		.clk(CLOCK_50),
+		.clock(CLOCK_50),
 		.rst(SW[0]),
-		.mode(SW[1])
+		.mode(SW[1]),
+		.pc_if(),
+		.instruction_if(),
+		.mem0(),
+		.mem1(),
+		.mem2(),
+		.mem3(),
+		.mem4(),
+		.mem5(),
+		.mem6()
 	);
-
+	
 	assign LEDG[0] = SW[0];
 	assign LEDG[1] = SW[1];
 

Codes/ARM_Testbench.v

@@ -1,8 +1,8 @@
-`timescale 1ps/1ps
+`timescale 1ns/1ns
 module ARM_Testbench();
-    reg clk, rst, mode;
-
-    ARM_cpu ARM_PROCESSOR(clk, rst, mode);
+        reg clk, rst, mode;
+        wire [31:0]mem0, mem1, mem2, mem3, mem4, mem5, mem6;
+    ARM_cpu arm(clk, rst, mode,,,mem0, mem1, mem2, mem3, mem4, mem5, mem6);
 
     initial begin
         rst = 1'b1;

Codes/ARM_cpu.v

@@ -1,10 +1,12 @@
 module ARM_cpu (
-    clk, rst, mode
+    clock, rst, mode,
+    pc_if, instruction_if,
+    mem0,mem1,mem2,mem3,mem4,mem5,mem6
 );
-    input clk, rst, mode;
+    input clock, rst, mode;
+    output [31:0] pc_if, instruction_if,mem0,mem1,mem2,mem3,mem4,mem5,mem6;
 
     wire [31:0] branch_addr;
-    wire [31:0] pc_if, instruction_if;
     wire [31:0] pc_id, instruction_id;
     wire [31:0] pc_exe;
     wire [3:0] status_bits_in, status_bits_out;
@@ -33,6 +35,13 @@ module ARM_cpu (
     wire [31:0] fu_val_rm;
 
     assign hazard = (hazard1 & ~mode) | (hazard2 & mode);
+    reg clk;
+    always@(posedge clock, posedge rst)begin
+        if(rst == 1'b1)
+            clk <= 1'b0;
+        else
+		    clk <= ~clk;
+	end
 
     IF_Stage if_stage (
         .clk(clk),
@@ -210,7 +219,8 @@ module ARM_cpu (
         .mem_write(mem_w_en_mem),
         .address(alu_res_mem-32'd1024),
         .data(val_rm_mem),
-        .mem_result(mem_res)
+        .mem_result(mem_res),
+        .mem0(mem0), .mem1(mem1), .mem2(mem2), .mem3(mem3), .mem4(mem4), .mem5(mem5), .mem6(mem6)
     );
 
     MEM_Stage_Reg memory_stage_reg(

Codes/ConditionCheck.v

@@ -31,6 +31,7 @@ module ConditionCheck (
             4'b1100: cond_out = (z == 1'b0 && n == v);
             4'b1101: cond_out = (z == 1'b1 && n != v);
             4'b1110: cond_out = 1'b1;
+            default: cond_out = 1'b1;
         endcase
     end
 

Codes/ControlUnit.v

@@ -44,5 +44,4 @@ module ControlUnit (
             exe_cmd = 4'b0000;
     end
 
-
 endmodule

Codes/Hazard_Detection_Unit.v

@@ -37,4 +37,4 @@ module Hazard_Detection_Unit (
         end
     end
 
-endmodule
+endmodule

Codes/ID_Stage.v

@@ -92,5 +92,4 @@ module ID_Stage (
         .reg2(val_rm)
     );
 
-
 endmodule

Codes/InstMemory.v

@@ -53,11 +53,19 @@ module InstMemory (
 
 		mem[40] = 32'b1110_01_0_0100_1_0000_0001_000000000000; //LDR R1 ,[R0],#0 //R1 = -2147483648
 		mem[41] = 32'b1110_01_0_0100_1_0000_0010_000000000100; //LDR R2 ,[R0],#4 //R2 = -1073741824
-		mem[42] = 32'b1110_01_0_0100_1_0000_0011_000000001000; //STR R3 ,[R0],#8 //R3 = 41	
-		mem[43] = 32'b1110_01_0_0100_1_0000_0100_000000001100; //STR R4 ,[R0],#12 //R4 = 8192
-		mem[44] = 32'b1110_01_0_0100_1_0000_0101_000000010000; //STR R5 ,[R0],#16 //R5 = -123
-		mem[45] = 32'b1110_01_0_0100_1_0000_0110_000000010100; //STR R6 ,[R0],#20 //R4 = 10	
-		mem[46] = 32'b1110_10_1_0_111111111111111111111111 ;   //B #-1
+		mem[42] = 32'b1110_01_0_0100_1_0000_0011_000000001000; //LDR R3 ,[R0],#8 //R3 = -123
+		mem[43] = 32'b1110_01_0_0100_1_0000_0100_000000001100; //LDR R4 ,[R0],#12 //R4 = -123
+		mem[44] = 32'b1110_01_0_0100_1_0000_0101_000000010000; //LDR R5 ,[R0],#16 //R5 = 10
+		mem[45] = 32'b1110_01_0_0100_1_0000_0110_000000010100; //LDR R6 ,[R0],#20 //R6 = 41	
+		mem[46] = 32'b1110_01_0_0100_1_0000_0111_000000011000; //LDR R7 ,[R0],#24 //R7 = 8912
+		mem[47] = 32'b1110_00_1_1101_0_0000_1000_000000000000; //MOV R8 ,#0 //R8 = 0
+		mem[48] = 32'b1110_00_1_1101_0_0000_1001_000000000000; //MOV R9 ,#0 //R9 = 0
+		mem[49] = 32'b1110_00_1_1101_0_0000_1010_000000000000; //MOV R10 ,#0 //R10 = 0
+		mem[50] = 32'b1110_00_1_1101_0_0000_1011_000000000000; //MOV R11 ,#0 //R11 = 0
+		mem[51] = 32'b1110_00_1_1101_0_0000_1100_000000000000; //MOV R12 ,#0 //R12 = 0
+		mem[52] = 32'b1110_00_1_1101_0_0000_1101_000000000000; //MOV R13 ,#0 //R13 = 0
+		mem[53] = 32'b1110_00_1_1101_0_0000_1110_000000000000; //MOV R14 ,#0 //R14 = 0
+		mem[54] = 32'b1110_10_1_0_111111111111111111111111 ;   //B #-1
 	end
 
 	assign Inst = mem[AddrIn[17:2]];

Codes/Memory.v

@@ -2,22 +2,38 @@ module Memory (
     clk, rst,
     mem_read, mem_write,
     address, data,
-    mem_result
+    mem_result,
+    mem0, mem1, mem2, mem3, mem4, mem5, mem6
 );
     input clk, rst;
     input mem_read, mem_write;
     input [31:0] address, data;
     output [31:0] mem_result;
+
+    output [31:0] mem0, mem1, mem2, mem3, mem4, mem5, mem6;
 
     reg [31:0] mem[0:63];
 
+    integer i;
     // Divide address into 4 to align the memory
 	assign mem_result = (mem_read == 1'b1) ? mem[address >> 2] : 32'b0;
 
-    always @(posedge clk) begin
-        if (mem_write == 1'b1) begin
+    always @(posedge clk, posedge rst) begin
+        if(rst == 1'b1) begin
+            for(i=0; i<64; i=i+1)
+                mem[i] <= 32'b0;
+        end
+        else if(mem_write == 1'b1) begin
             mem[address >> 2] <= data;
         end
     end
 
+    assign mem0 = mem[0];
+    assign mem1 = mem[1];
+    assign mem2 = mem[2];
+    assign mem3 = mem[3];
+    assign mem4 = mem[4];
+    assign mem5 = mem[5];
+    assign mem6 = mem[6];
+
 endmodule

Codes/Q_ARM_Testbench.v

@@ -0,0 +1,26 @@
+`timescale 1ns/1ns
+module Q_ARM_Testbench();
+    reg clk, rst, mode;
+    wire [31:0] mem0, mem1, mem2, mem3, mem4, mem5, mem6;
+    wire [31:0] pc_if, instruction_if;
+
+    ARM_cpu_ arm (
+        clk, rst, mode,
+        pc_if, instruction_if,
+        mem0, mem1, mem2, mem3, mem4, mem5, mem6
+    );
+
+    initial begin
+        rst = 1'b1;
+        clk = 1'b0;
+        mode = 1'b1;
+        #20 rst = 1'b0;
+        #20000;
+        $stop;
+    end
+
+    always begin
+        #10 clk = ~clk;
+    end
+
+endmodule

Codes/RegisterFile.v

@@ -8,7 +8,7 @@ module RegisterFile (
     input clk, rst;
     input [3:0] src1, src2, Dest_wb;
     input [31:0] Result_WB;
-    output writeBackEn;
+    input writeBackEn;
     output [31:0] reg1, reg2;
 
     reg [31:0] register_file[0:15];

Codes/Status_Reg.v

@@ -10,10 +10,12 @@ module Status_Reg(
     always @(negedge clk, posedge rst) begin
         if (rst == 1'b1)
             d_out <= 4'b0;
-        else if(ld == 1'b1)
-            d_out <= d_in;
-        else
-            d_out <= d_out;
+        else begin
+            if(ld == 1'b1)
+                d_out <= d_in;
+            else
+                d_out <= d_out;
+        end
     end
-  
+
 endmodule

Codes/Val2_Ganerator.v

@@ -10,16 +10,15 @@ module Val2_Generator (
 	input [31:0] val_rm;
 	output reg [31:0] val2;
 
-	reg [63:0] rotate_wire;
-	reg [63:0] immd;
-	reg [4:0] shift_im;
-	reg [4:0] rotate_im;
+	wire [63:0] rotate_wire;
+	wire [63:0] immd;
+	wire [4:0] rotate_im;
 
+	assign immd = {{24{shift_operand[7]}} , shift_operand[7:0] , {24{shift_operand[7]}} , shift_operand[7:0]};
+	assign rotate_im = {shift_operand[11:8] , 1'b0};
+	assign rotate_wire = {val_rm , val_rm};
+
 	always @(shift_operand, imm, val_rm, control_input) begin
-		immd = {{24{shift_operand[7]}} , shift_operand[7:0] , {24{shift_operand[7]}} , shift_operand[7:0]};
-		rotate_im = {shift_operand[11:8] , 1'b0};
-		rotate_wire = {val_rm , val_rm};
-		shift_im = shift_operand[11:7];
 		if (control_input == 1'b1) begin
 			val2 <= {{20{shift_operand[11]}}, shift_operand};
 		end
@@ -28,13 +27,12 @@ module Val2_Generator (
 				2'b00 : val2 <= (val_rm << shift_operand[11:7]);
 				2'b01 : val2 <= (val_rm >> shift_operand[11:7]);
 				2'b10 : val2 <= (val_rm >>> shift_operand[11:7]);
-				2'b11 : val2 <= (rotate_wire >> shift_im);
+				2'b11 : val2 <= (rotate_wire >> shift_operand[11:7]);
 			endcase
 		end
 		else if(imm == 1'b1) begin
 			val2 <= (immd >> rotate_im);
 		end
 	end
-
-
+
 endmodule